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    SEMICONDUCTOR DEVICE INCLUDING BIT LINE
    1.
    发明申请
    SEMICONDUCTOR DEVICE INCLUDING BIT LINE 有权

    公开(公告)号：US20250063725A1

    公开(公告)日：2025-02-20

    申请号：US18656933

    申请日：2024-05-07

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin KIM ,  Seungbo KO ,  Donghyuk AHN ,  Minyoung LEE

    IPC: H10B12/00 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor device may include first and second bit lines that each include a line portion, a connection portion extending from the line portion into a first extension region, and a pad portion extending from the connection portion in the first extension region; and a third bit line between the line portions of the first and second bit lines in a memory cell array region and the first extension region. A first end portion of the third bit line may be in the first extension region. The pad portions of the first and second bit lines each may be wider than the line portions of the first and second bit lines. A minimum distance between the pad portions of the first and second bit lines may be less than a minimum distance between the line portion of the first bit line and the third bit line.

    SEMICONDUCTOR DEVICE
    3.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240321735A1

    公开(公告)日：2024-09-26

    申请号：US18601467

    申请日：2024-03-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Seungbo KO ,  Sujin KANG ,  Jongmin KIM ,  Donghyuk AHN ,  Jiwon OH ,  Chansic YOON ,  Myeongdong LEE ,  Minyoung LEE ,  Inho CHA

    IPC: H01L23/528 ,  H10B12/00

    CPC classification number: H01L23/528 ,  H10B12/00

    Abstract: A semiconductor device includes a substrate, a word line extending on the substrate in a first horizontal direction, a bit line extending on the substrate in a second horizontal direction perpendicular to the first horizontal direction, and a spacer structure on one sidewall of the bit line, wherein the bit line includes a lower conductive layer, an intermediate conductive layer, and an upper conductive layer stacked in a vertical direction on the substrate, and the spacer structure includes a depletion stopping layer on one sidewall of the lower conductive layer, extending in the vertical direction and including a material layer having an interfacial trap density less than an interfacial trap density of a silicon nitride layer, and an inner spacer extending in the vertical direction and on one sidewall of the depletion stopping layer.

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