公开(公告)号：US12101923B2

公开(公告)日：2024-09-24

申请号：US18207689

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewha Park ,  Moonkeun Kim ,  Sukhoon Kim ,  Dongchan Lim

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

公开(公告)号：US11764145B2

公开(公告)日：2023-09-19

申请号：US17223144

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaejin Lee ,  Hana Kim ,  Jaewha Park ,  Dongchan Lim

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5226 ,  H01L21/76841 ,  H01L21/76877 ,  H01L23/528 ,  H01L23/53238

Abstract: A wiring structure includes a filling metal, a cover metal including cobalt (Co) on the filling metal, the cover metal having a first portion along a side surface and along a lower surface of the filling metal, and a second portion along an upper surface of the filling metal, a barrier metal on an outer surface of the first portion of the cover metal, and a capping metal on an outer surface of the second portion of the cover metal, the capping metal including a cobalt (Co) alloy, wherein the filling metal has higher conductivity than the cover metal and the barrier metal.

公开(公告)号：US11700722B2

公开(公告)日：2023-07-11

申请号：US17520868

申请日：2021-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewha Park ,  Moonkeun Kim ,  Sukhoon Kim ,  Dongchan Lim

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

公开(公告)号：US20240105425A1

公开(公告)日：2024-03-28

申请号：US18244571

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungwan Yoo ,  Jeongyeon Lee ,  Dohyung Kim ,  Jaehong Park ,  Dongchan Lim

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01J37/32422 ,  H01J37/32522 ,  H01J37/32568 ,  H01J37/32715 ,  H01L21/02274 ,  H01L21/67098

Abstract: A substrate processing apparatus including a first chamber configured to accommodate a substrate therein and a second chamber including a heater provided in an internal space thereof, wherein the first chamber includes a target assembly configured to fix a target including a deposition material, a first ion gun configured to irradiate an ion beam onto the target to discharge deposition particles, which are ions of the deposition material, to the substrate, and a second ion gun configured to irradiate a hydrogen ion beam toward the substrate, the second ion gun includes a plasma generator configured to generate plasma, and a first grid electrode and a second grid electrode each configured to extract ions from the container, and the second chamber is configured to be provided with the substrate, on which the hydrogen ion beam has been irradiated, and perform thermal treatment on the substrate.