公开(公告)号：US20160099243A1

公开(公告)日：2016-04-07

申请号：US14736441

申请日：2015-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  Sharma DEEPAK ,  Chulhong PARK

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.

Abstract translation: 半导体器件及其制造方法包括在与第一方向相交的第二方向上在第一方向上延伸并彼此间隔开的第一和第二栅极结构，设置在第一和第二栅极结构之间的虚拟栅极结构 在第一栅极结构和伪栅极结构之间的第一源极/漏极区域，在第二栅极结构和伪栅极结构之间的第二源极/漏极区域，设置在虚拟栅极结构上的连接接触点以及公共导线 提供在连接接点上。 虚拟栅极结构沿第一方向延伸。 连接触头沿第二方向延伸以将第一源极/漏极区域连接到第二源极/漏极区域。 所述公共导线被配置为通过所述连接触点对所述第一和第二源/漏区的电压。

公开(公告)号：US20150084097A1

公开(公告)日：2015-03-26

申请号：US14312702

申请日：2014-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sooyeon JEON ,  Rwik SENGUPTA ,  Chulhong PARK ,  Kwanyoung CHUN ,  Yusun LEE ,  Hyun-Jong LEE

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L2027/11861 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate on which a plurality of logic cells are provided, and a plurality of active portions provided on the substrate and extending in a first direction. Contacts and gate structures extend in a second direction intersecting the first direction and are alternately arranged. A common conductive line extends along a boundary region of the plurality of logic cells in the first direction. At least one of the contacts is electrically connected to the common conductive line through a via therebetween, and each of the contacts intersects a plurality of the active portions. End portions of the contacts are aligned with each other along the first direction.

Abstract translation: 半导体器件包括其上设置有多个逻辑单元的基板和设置在基板上并沿第一方向延伸的多个有源部分。 触点和栅极结构在与第一方向相交的第二方向上延伸并且交替地布置。 公共导线沿第一方向沿多个逻辑单元的边界区域延伸。 至少一个触点通过它们之间的通孔电连接到公共导线，并且每个触点与多个有源部分相交。 触点的端部沿着第一方向彼此对准。

公开(公告)号：US20190286785A1

公开(公告)日：2019-09-19

申请号：US16432139

申请日：2019-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjun PARK ,  Byung-Sung KIM ,  Chulhong PARK ,  Chunyub PARK

IPC: G06F17/50 ,  H01L27/02

Abstract: A design method of a semiconductor integrated circuit layout and a method of fabricating a semiconductor device, the design method including selecting a first cell layout including at least one first gate pattern; selecting a second cell layout including at least one second gate pattern, the at least one second gate pattern having a gate length that is different from a gate length of the at least one first gate pattern; producing a pattern layout from the first and second cell layouts; and producing a mask layout selectively overlapping the first cell layout on the pattern layout.

公开(公告)号：US20160322355A1

公开(公告)日：2016-11-03

申请号：US15206610

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Raheel AZMAT ,  Sharma DEEPAK ,  Chulhong PARK

IPC: H01L27/088 ,  H01L23/522 ,  H01L29/08 ,  H01L27/02 ,  H01L23/528 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823821 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0847 ,  H01L2027/11829 ,  H01L2027/11875

Abstract: A semiconductor device, and a method of manufacturing the same, includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a dummy gate structure provided between the first and second gate structures, a first source/drain region between the first gate structure and the dummy gate structure, a second source/drain region between the second gate structure and the dummy gate structure, a connection contact provided on the dummy gate structure, and a common conductive line provided on the connection contact. The dummy gate structure extends in the first direction. The connection contact extends in the second direction to connect the first source/drain region to the second source/drain region. The common conductive line configured to a voltage to the first and second source/drain regions through the connection contact.