公开(公告)号：US11537041B2

公开(公告)日：2022-12-27

申请号：US16937266

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulho Kim ,  Chorong Park ,  Soohan Kim ,  Junghoon Kim ,  Jeonghun Park

IPC: G03F1/42 ,  H01L21/66 ,  H01L21/027 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor device includes: forming a first outer box and a second outer box on a wafer, providing a photoresist layer on the wafer; and by removing a portion of the photoresist layer, forming a photoresist pattern including a first opening and a second opening that are horizontally apart from each other, wherein the first opening defines a first inner box superimposed on the first outer box in a plan view, the second opening defines a second inner box superimposed on the second outer box in the plan view, and a horizontal distance between the first opening and the second opening is about 150 μm to about 400 μm.

公开(公告)号：US20210132489A1

公开(公告)日：2021-05-06

申请号：US16937266

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulho Kim ,  Chorong Park ,  Soohan Kim ,  Junghoon Kim ,  Jeonghun Park

IPC: G03F1/42 ,  H01L21/66 ,  H01L23/544 ,  H01L21/027

Abstract: A method of manufacturing a semiconductor device includes: forming a first outer box and a second outer box on a wafer, providing a photoresist layer on the wafer; and by removing a portion of the photoresist layer, forming a photoresist pattern including a first opening and a second opening that are horizontally apart from each other, wherein the first opening defines a first inner box superimposed on the first outer box in a plan view, the second opening defines a second inner box superimposed on the second outer box in the plan view, and a horizontal distance between the first opening and the second opening is about 150 μm to about 400 μm.

公开(公告)号：US10917098B2

公开(公告)日：2021-02-09

申请号：US16704486

申请日：2019-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehyuk Jang ,  Sangwook Han ,  Shinwoong Kim ,  Jaeyoung Kim ,  Chulho Kim

IPC: H03D3/24 ,  H03L7/089 ,  H04B3/52 ,  H03L7/099 ,  H04B3/54 ,  H04L7/033 ,  H03L7/087

Abstract: A device for wireless communication using a plurality of antennas including a first local oscillation generator configured to generate a first local oscillation signal for up-converting a first transmission signal, a second local oscillation generator configured to generate a second local oscillation signal for up-converting a second transmission signal, and a phase difference detector configured to, detect a first phase difference between the first local oscillation signal and the second local oscillation signal, and generate a first phase compensation signal based on the first phase difference for adjusting a phase of at least one of the first transmission signal or the second transmission signal.

公开(公告)号：US10897259B1

公开(公告)日：2021-01-19

申请号：US16853076

申请日：2020-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shinwoong Kim ,  Myounggyun Kim ,  Chulho Kim ,  Inhyo Ryu ,  Jaewon Choi ,  Sangwook Han ,  Honggul Han

IPC: H03L7/087 ,  H03L7/089 ,  H03L7/095 ,  H03L7/14 ,  H03L7/091 ,  H03L7/099 ,  H03L7/195 ,  H03L7/093

Abstract: A phase locked circuit includes an oscillator configured to generate an output clock signal, a first phase detector configured to detect a phase difference between an input clock signal and a feedback clock signal based on the output clock signal, a second phase detector having a wider phase locking range than that of the first phase detector and configured to detect the phase difference between the input clock signal and the feedback clock signal, and a charge pump controller configured to control an output current of a charge pump included in the second phase detector based on the phase difference detected by the first phase detector. When the phase difference between the input clock signal and the feedback clock signal is within the phase locking range of the first phase detector, the oscillator and the first phase detector are connected to each other.

公开(公告)号：US09240165B2

公开(公告)日：2016-01-19

申请号：US13785832

申请日：2013-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Kon Bae ,  Dokyung Kim ,  Chulho Kim ,  Junho Park ,  Sooyoung Woo ,  Chiho Cha ,  Jeung Hwan Lee

IPC: G09G5/39 ,  G09G5/00 ,  G09G5/393 ,  G09G5/18

CPC classification number: G09G5/39 ,  G09G5/006 ,  G09G5/18 ,  G09G5/393 ,  G09G2370/08

Abstract: A display driver integrated circuit which includes a distributor configured to output display data; a plurality of first-in first-out (FIFO) memories configured to receive the display data from the distributor according to an external clock and output the display data in response to an internal clock; and a plurality of graphics memories configured to receive the display data from the FIFO memories.

Abstract translation: 一种显示驱动器集成电路，包括配置成输出显示数据的分配器; 多个先进先出（FIFO）存储器，被配置为根据外部时钟从分配器接收显示数据，并响应于内部时钟输出显示数据; 以及配置成从FIFO存储器接收显示数据的多个图形存储器。