公开(公告)号：US11805710B2

公开(公告)日：2023-10-31

申请号：US17395043

申请日：2021-08-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Heejung Kim ,  Taehong Min ,  Chorong Park ,  Joohee Seo ,  Eunsuk Hwang

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H10N70/063 ,  H10B63/84 ,  H10N70/068

Abstract: A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.

公开(公告)号：US20140329379A1

公开(公告)日：2014-11-06

申请号：US14085194

申请日：2013-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chul-Ho Kim ,  Cheolhong Kim ,  Chorong Park ,  Jaehan Lee

IPC: H01L21/308 ,  H01L21/283 ,  H01L21/28

CPC classification number: H01L21/283 ,  H01L21/0274 ,  H01L21/0335 ,  H01L21/28008 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76838 ,  H01L27/11548 ,  H01L27/11575 ,  H01L2221/1021

Abstract: A patterning method includes forming a photoresist layer on a processing layer and exposing the photoresist layer using a standing wave/defocusing exposure to produce a photoresist layer having a staircase pattern.

Abstract translation: 图案化方法包括在处理层上形成光致抗蚀剂层，并使用驻波/散焦曝光曝光光致抗蚀剂层，以产生具有阶梯图案的光致抗蚀剂层。

公开(公告)号：US11796923B2

公开(公告)日：2023-10-24

申请号：US17392788

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjay Kang ,  Chorong Park ,  Doogyu Lee ,  Seungyoon Lee ,  Jeongjin Lee

IPC: G03F7/20 ,  G03F7/00 ,  G03F1/70

CPC classification number: G03F7/70633 ,  G03F7/2004 ,  G03F1/70

Abstract: Disclosed are an overlay correction method, a method of evaluating an overlay correction operation, and a method of fabricating a semiconductor device using the overlay correction method. The overlay correction method may include measuring an overlay between center lines of lower and upper patterns on a wafer, fitting each of components of the overlay with a polynomial function to obtain first fitting quantities, and summing the first fitting quantities to construct a correction model. The components of the overlay may include overlay components, which are respectively measured in two different directions parallel to a top surface of a reticle. The highest order of the polynomial function may be determined as an order, which minimizes a difference between the polynomial function and each of the components of the overlay or corresponds to an inflection point in a graph of the difference with respect to the highest order of the polynomial function.

公开(公告)号：US11537041B2

公开(公告)日：2022-12-27

申请号：US16937266

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulho Kim ,  Chorong Park ,  Soohan Kim ,  Junghoon Kim ,  Jeonghun Park

IPC: G03F1/42 ,  H01L21/66 ,  H01L21/027 ,  H01L23/544

Abstract: A method of manufacturing a semiconductor device includes: forming a first outer box and a second outer box on a wafer, providing a photoresist layer on the wafer; and by removing a portion of the photoresist layer, forming a photoresist pattern including a first opening and a second opening that are horizontally apart from each other, wherein the first opening defines a first inner box superimposed on the first outer box in a plan view, the second opening defines a second inner box superimposed on the second outer box in the plan view, and a horizontal distance between the first opening and the second opening is about 150 μm to about 400 μm.

公开(公告)号：US20210132489A1

公开(公告)日：2021-05-06

申请号：US16937266

申请日：2020-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chulho Kim ,  Chorong Park ,  Soohan Kim ,  Junghoon Kim ,  Jeonghun Park

IPC: G03F1/42 ,  H01L21/66 ,  H01L23/544 ,  H01L21/027

Abstract: A method of manufacturing a semiconductor device includes: forming a first outer box and a second outer box on a wafer, providing a photoresist layer on the wafer; and by removing a portion of the photoresist layer, forming a photoresist pattern including a first opening and a second opening that are horizontally apart from each other, wherein the first opening defines a first inner box superimposed on the first outer box in a plan view, the second opening defines a second inner box superimposed on the second outer box in the plan view, and a horizontal distance between the first opening and the second opening is about 150 μm to about 400 μm.