公开(公告)号：US11805710B2

公开(公告)日：2023-10-31

申请号：US17395043

申请日：2021-08-05

申请人： Samsung Electronics Co., Ltd.

发明人： Heejung Kim ,  Taehong Min ,  Chorong Park ,  Joohee Seo ,  Eunsuk Hwang

IPC分类号： H10N70/00 ,  H10B63/00

CPC分类号： H10N70/063 ,  H10B63/84 ,  H10N70/068

摘要： A method of fabricating a three-dimensional semiconductor memory device includes forming a cell stack layer covering key and cell regions of a substrate and including a variable resistance layer and a switching layer, forming key mask patterns on the cell stack layer of the key region and cell mask patterns on the cell stack layer of the cell region, and simultaneously forming a plurality of key patterns on the key region and a plurality of memory cells on the cell region by etching the cell stack layer using the key and cell mask patterns as an etching mask. Each memory cell includes a variable resistance pattern and a switching pattern formed by etching the variable resistance layer and the switching layer. Each key pattern includes a dummy variable resistance pattern and a dummy switching pattern formed by etching the variable resistance layer and the switching layer.