公开(公告)号：US11796923B2

公开(公告)日：2023-10-24

申请号：US17392788

申请日：2021-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjay Kang ,  Chorong Park ,  Doogyu Lee ,  Seungyoon Lee ,  Jeongjin Lee

IPC: G03F7/20 ,  G03F7/00 ,  G03F1/70

CPC classification number: G03F7/70633 ,  G03F7/2004 ,  G03F1/70

Abstract: Disclosed are an overlay correction method, a method of evaluating an overlay correction operation, and a method of fabricating a semiconductor device using the overlay correction method. The overlay correction method may include measuring an overlay between center lines of lower and upper patterns on a wafer, fitting each of components of the overlay with a polynomial function to obtain first fitting quantities, and summing the first fitting quantities to construct a correction model. The components of the overlay may include overlay components, which are respectively measured in two different directions parallel to a top surface of a reticle. The highest order of the polynomial function may be determined as an order, which minimizes a difference between the polynomial function and each of the components of the overlay or corresponds to an inflection point in a graph of the difference with respect to the highest order of the polynomial function.