公开(公告)号：US20220321125A1

公开(公告)日：2022-10-06

申请号：US17591093

申请日：2022-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Daehyun KWON ,  Hyejung KWON ,  Hyeran KIM ,  Chisung OH

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17772 ,  H03K19/17736

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

公开(公告)号：US20240201868A1

公开(公告)日：2024-06-20

申请号：US18588599

申请日：2024-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.

公开(公告)号：US20190237390A1

公开(公告)日：2019-08-01

申请号：US16263408

申请日：2019-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung RHO ,  Chisung OH ,  Kyomin SOHN ,  Yong-Ki KIM ,  Jong-Ho MOON ,  SeungHan WOO ,  Jaeyoun YOUN

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538

Abstract: A semiconductor device includes first to M-th semiconductor dies stacked in a first direction. Each of the first to M-th semiconductor dies includes a substrate, first to K-th through silicon vias passing through the substrate in the first direction, and a first circuit to receive power through a power supply line electrically connected to the first through silicon via. Each of first to K-th through silicon vias of the N-th semiconductor die is electrically connected to a through silicon via of first to K-th through silicon vias of the (N+1)-th semiconductor die that is spaced apart therefrom in a plan view.

公开(公告)号：US20240120921A1

公开(公告)日：2024-04-11

申请号：US18390224

申请日：2023-12-20

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Daehyun KWON ,  Hyejung KWON ,  Hyeran KIM ,  Chisung OH

IPC: H03K19/017 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/17772

CPC classification number: H03K19/01742 ,  H03K19/0005 ,  H03K19/1774 ,  H03K19/17772

Abstract: An apparatus, a memory device, and a method for storing parameter codes with respect to asymmetric on-die-termination (ODT) are provided. The apparatus is connected to an external device via a signal line, and includes: an on-die termination (ODT) circuit set in a first ODT state; a plurality of signal pins, each of which is connected to the signal line; and an ODT control circuit configured to: identify whether a second ODT state of the external device corresponds to the first ODT state, and based on the apparatus being an asymmetric ODT in which the first ODT state and the second ODT state are different, provide an asymmetric ODT parameter code to the external device, and disable the ODT circuit when a signal is not transmitted through the signal line.

公开(公告)号：US20230344444A1

公开(公告)日：2023-10-26

申请号：US17975034

申请日：2022-10-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changkyu SEOL ,  Sungrae KIM ,  Chisung OH ,  Junghwan CHOI

IPC: H03M5/14 ,  H04L1/00

CPC classification number: H03M5/145 ,  H04L1/0009 ,  H04L1/0014

Abstract: A transmitter includes an encoder configured to divide a first number of binary input bits of an input data signal into a first bit group and a second bit group, generate a first intermediate bit group and a second intermediate bit group by manipulating the first bit group and the second bit group differently based on a value of the first bit group, and generate a first symbol group and a second symbol group by encoding the first intermediate bit group and the second intermediate bit group, each of the first symbol group and the second symbol group including a plurality of symbols, and each of the plurality of symbols having three different voltage levels. The transmitter includes a driver configured to generate an output data signal by concatenating the first symbol group and the second symbol group.

公开(公告)号：US20220382464A1

公开(公告)日：2022-12-01

申请号：US17743137

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungrae KIM ,  Hyeran KIM ,  Myungkyu LEE ,  Chisung OH ,  Kijun LEE ,  Sunghye CHO ,  Sanguhn CHA

IPC: G06F3/06

Abstract: A semiconductor memory device includes a memory cell array and a cyclic redundancy check (CRC) engine. The memory cell array includes a plurality of volatile memory cells coupled to respective ones of a plurality of word-lines and respective ones of a plurality of bit-lines. The CRC engine, during a memory operation on the memory cell array, detects an error in a main data and a system parity data provided from a memory controller external to the semiconductor memory device through a link, generates an error flag indicating whether the detected error corresponds to either a first type of error associated with the link or a second type of error associated with the volatile memory cells based on the system parity data and transmit the error flag to the memory controller.