公开(公告)号：US09496381B2

公开(公告)日：2016-11-15

申请号：US13716402

申请日：2012-12-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mongsup Lee ,  Yoonho Son ,  Woogwan Shim ,  Chan Min Lee ,  Inseak Hwang

IPC: H01L29/78 ,  H01L27/108

CPC classification number: H01L29/78 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888

Abstract: A semiconductor device may include a substrate including an active pattern delimited by a device isolation pattern, a gate electrode crossing the active pattern, a first impurity region and a second impurity region in the active pattern on both sides of the gate electrode, a bit line crossing the gate electrode, a first contact electrically connecting the first impurity region with the bit line, and a first nitride pattern on a lower side surface of the first contact. A width of the first contact measured perpendicular to an extending direction of the bit line may be substantially equal to that of the bit line.

Abstract translation: 半导体器件可以包括：衬底，其包括由器件隔离图案限定的有源图案，与有源图案交叉的栅极电极，栅电极两侧的有源图案中的第一杂质区域和第二杂质区域，位线 跨越栅电极，将第一杂质区与位线电连接的第一接触和第一接触的下侧表面上的第一氮化物图案。 垂直于位线的延伸方向测量的第一接触件的宽度可以基本上等于位线的宽度。

公开(公告)号：US09947668B2

公开(公告)日：2018-04-17

申请号：US14591165

申请日：2015-01-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin Lee ,  Sungho Jang ,  Jiyoung Kim ,  Kang-Uk Kim ,  Chan Min Lee ,  Juyeon Jang

IPC: H01L27/108 ,  H01L21/3213

CPC classification number: H01L27/10885 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32139 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897

Abstract: Semiconductor devices, and methods for forming the same, include forming a first wiring film and an etching buffer film in a cell array region and a peripheral circuit region of a substrate, and forming a contact hole by selectively etching the etching buffer film and the first wiring film so as to expose an active region of the cell array region and at least a part of a field isolation region adjacent thereto. A bit line contact is formed in the contact hole to be in contact with the active region, and a second wiring film is formed over the substrate. By patterning the second wiring film, the bit line contact, the etching buffer film, and the first wiring film, a bit line is formed in the cell array region and a peripheral gate is formed in the peripheral circuit region.