公开(公告)号：US20180374825A1

公开(公告)日：2018-12-27

申请号：US16114795

申请日：2018-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Cha-jea JO ,  Soo-hyun HA

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/53238 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06582

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US20180145104A1

公开(公告)日：2018-05-24

申请号：US15636801

申请日：2017-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-hwang KIM ,  Jong-bo SHIM ,  Sang-uk HAN ,  Cha-jea JO ,  Won-il LEE

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14636

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

公开(公告)号：US20210217735A1

公开(公告)日：2021-07-15

申请号：US17213715

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Cha-jea JO ,  Soo-hyun HA

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US20200243488A1

公开(公告)日：2020-07-30

申请号：US16847987

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Cha-jea JO ,  Soo-hyun HA

IPC: H01L25/065 ,  H01L23/532 ,  H01L23/31

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US20170338206A1

公开(公告)日：2017-11-23

申请号：US15421386

申请日：2017-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Cha-jea JO ,  Soo-hyun HA

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L25/0657 ,  H01L23/3185 ,  H01L23/53238 ,  H01L2224/16145 ,  H01L2224/73204 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06582

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US20230238417A1

公开(公告)日：2023-07-27

申请号：US18127110

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-hwang KIM ,  Jong-bo SHIM ,  Sang-uk HAN ,  Cha-jea JO ,  Won-il LEE

IPC: H01L27/146

CPC classification number: H01L27/14634 ,  H01L27/1462 ,  H01L27/14636 ,  H01L27/14638

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

公开(公告)号：US20170229412A1

公开(公告)日：2017-08-10

申请号：US15494942

申请日：2017-04-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Seung-kwan RYU ,  Cha-jea JO ,  Tae-Je CHO

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/481 ,  H01L23/562 ,  H01L24/11 ,  H01L24/13 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/02331 ,  H01L2224/02375 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/05024 ,  H01L2224/05025 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13018 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/13026 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/1415 ,  H01L2224/14181 ,  H01L2224/14519 ,  H01L2224/16146 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2224/17519 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06565 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/00014

Abstract: The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.

公开(公告)号：US20210202563A1

公开(公告)日：2021-07-01

申请号：US17202702

申请日：2021-03-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-hwang KIM ,  Jong-bo SHIM ,  Sang-uk HAN ,  Cha-jea JO ,  Won-il LEE

IPC: H01L27/146

Abstract: An image sensor package includes an image sensor chip on a package substrate, a logic chip on the package substrate and perpendicularly overlapping the image sensor chip, and a memory chip on the package substrate and perpendicularly overlapping the image sensor chip and logic chip. The logic chip processes a pixel signal output from the image sensor chip. The memory chip is electrically connected to the image sensor chip through a conductive wire and stores at least one of the pixel signal from the image sensor chip or a pixel signal processed by the logic chip. The memory chip receives the pixel signal output from the image sensor chip through the conductive wire and receives the pixel signal processed by the logic chip through the image sensor chip and the conductive wire.

公开(公告)号：US20200286862A1

公开(公告)日：2020-09-10

申请号：US16881767

申请日：2020-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Cha-jea JO ,  Soo-hyun HA

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/532

Abstract: A semiconductor package includes a first semiconductor chip in which a through-electrode is provided, a second semiconductor chip connected to a top surface of the first semiconductor chip, a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.

公开(公告)号：US20190312013A1

公开(公告)日：2019-10-10

申请号：US16448703

申请日：2019-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-kyoung SEO ,  Cha-jea JO ,  Soo-hyun HA

IPC: H01L25/065 ,  H01L23/532 ,  H01L23/31

Abstract: A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer, and a second connection hump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.