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1.发明申请公开(公告)号：US20200371157A1
公开(公告)日：2020-11-26
申请号：US16665318
申请日：2019-10-28
Applicant: Samsung Electronics Co., Ltd.
IPC: G01R31/28 , G01R31/317 , G01R31/3185
Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.
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2.发明申请METHOD OF PROGRAMMING FUSE CELLS AND REPAIRING MEMORY DEVICE USING THE PROGRAMMED FUSE CELLS 审中-公开使用编程保险丝细胞编程保险丝细胞和修复记忆装置的方法公开(公告)号：US20150049546A1
公开(公告)日：2015-02-19
申请号：US14306851
申请日：2014-06-17
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ahn Choi
IPC: G11C29/00 , H01L23/525 , G11C17/16
CPC classification number: G11C17/16 , G11C29/785
Abstract: A plurality of fuse cells includes a first fuse cell and a second fuse cell. Each of the first and second fuse cells includes a first anti-fuse and a second anti-fuse. A method of programming the fuse cells includes rupturing the first anti-fuse of the first fuse cell based on first data loaded to a program control circuit. The method includes rupturing the second anti-fuse of the first fuse cell before loading second data to the program control circuit. The second data is for rupturing the first anti-fuse of the second fuse cell or the second anti-fuse of the second fuse cell.
Abstract translation: 多个熔丝单元包括第一熔丝单元和第二熔丝单元。 第一和第二熔丝单元中的每一个包括第一反熔丝和第二反熔丝。 一种编程熔丝单元的方法包括：基于加载到程序控制电路的第一数据来破坏第一熔丝单元的第一反熔丝。 该方法包括在将第二数据加载到程序控制电路之前，破坏第一熔丝单元的第二反熔丝。 第二数据用于破坏第二熔丝单元的第一反熔丝或第二熔丝单元的第二反熔丝。
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3.发明授权公开(公告)号：US12203980B2
公开(公告)日：2025-01-21
申请号：US18471624
申请日：2023-09-21
Applicant: Samsung Electronics Co., Ltd.
IPC: G01R31/28 , G01R31/317 , G01R31/3185
Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.
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4.发明授权公开(公告)号：US11867751B2
公开(公告)日：2024-01-09
申请号：US17872440
申请日：2022-07-25
Applicant: Samsung Electronics Co., Ltd.
IPC: G01R31/28 , G01R31/3185 , G01R31/317
CPC classification number: G01R31/2884 , G01R31/31715 , G01R31/318511
Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.
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Patent Agency Ranking
5.发明申请公开(公告)号：US20200027521A1
公开(公告)日：2020-01-23
申请号：US16245724
申请日：2019-01-11
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ahn Choi
IPC: G11C29/44 , G11C29/42 , G11C11/4097 , G11C17/16 , G11C7/18 , G11C7/22 , G11C8/14 , G11C5/02 , H01L23/538 , H01L27/115
Abstract: A stacked memory device includes a buffer die, a plurality of memory dies stacked on the buffer die and a plurality of through silicon vias (TSVs). The buffer die communicates with an external device. The TSVs extend through the plurality of memory dies to connect to the buffer die. Each of memory dies includes a memory cell array which includes a plurality of dynamic memory cells coupled to a plurality of word-lines and a plurality of bit-lines. The buffer die includes a test circuit, and the test circuit, in a test mode, performs a test on the dynamic memory cells of a target memory die corresponding to one of the memory dies and store, an address of a memory cell row including at least one defective cell, in at least one column decoder of other memory dies of except the target memory die.
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6.发明公开公开(公告)号：US20240012045A1
公开(公告)日：2024-01-11
申请号：US18471624
申请日：2023-09-21
Applicant: Samsung Electronics Co., Ltd.
IPC: G01R31/28 , G01R31/3185 , G01R31/317
CPC classification number: G01R31/2884 , G01R31/318511 , G01R31/31715
Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.
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7.发明申请公开(公告)号：US20220357393A1
公开(公告)日：2022-11-10
申请号：US17872440
申请日：2022-07-25
Applicant: Samsung Electronics Co., Ltd.
IPC: G01R31/28 , G01R31/3185 , G01R31/317
Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.
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8.发明申请ANTI-FUSE CIRCUIT OF SEMICONDUCTOR DEVICE AND METHODS OF TESTING INTERNAL CIRCUIT BLOCK THEREOF 审中-公开半导体器件的防熔丝电路及其内部电路块的测试方法公开(公告)号：US20130215696A1
公开(公告)日：2013-08-22
申请号：US13735094
申请日：2013-01-07
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ahn Choi , Kyung-Rak Choi
IPC: G11C29/04
CPC classification number: G11C29/04 , G11C17/00 , G11C17/16 , G11C29/026 , G11C29/027 , G11C29/028 , G11C29/24
Abstract: A method of testing an internal circuit block of anti-fuse circuit and a circuit for detecting a defect in the operation of the internal circuit block such as a defect in a sensing part or in a transfer part thereof. Forming a sensing part testing path in a sensing part connected to an output terminal of anti-fuse array; obtaining a sensing output signal through a sense amplifier in the sensing part by applying a test signal through the sensing part testing path while the anti-fuses in the anti-fuse array are not ruptured; detecting defects in the sensing part by comparing the sensing output signal with a reference data corresponding to the test signal. Defectively operating chips may be effectively repaired by adjusting control terminals within a specific control range upon detection of a defect of internal circuit block.
Abstract translation: 一种测试反熔丝电路的内部电路块的方法和用于检测内部电路块的操作中的缺陷的电路，例如感测部分或其传送部分中的缺陷。 在连接到反熔丝阵列的输出端子的感测部分中形成感测部件测试路径; 当反熔丝阵列中的防熔丝不破裂时，通过传感部件测试路径施加测试信号，通过感测部分中的感测放大器获得感测输出信号; 通过将感测输出信号与对应于测试信号的参考数据进行比较来检测感测部分中的缺陷。 在检测到内部电路块的缺陷时，可以通过在特定控制范围内调节控制端来有效地修复有缺陷的芯片。
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9.发明授权公开(公告)号：US11435397B2
公开(公告)日：2022-09-06
申请号：US16665318
申请日：2019-10-28
Applicant: Samsung Electronics Co., Ltd.
IPC: G01R31/28 , G01R31/3185 , G01R31/317
Abstract: A wafer-level method of testing an integrated circuit (IC) device includes: (i) applying a plurality of test operation signals to a wafer containing the IC device, (ii) generating a test enable signal in response to detecting, on the wafer, a toggling of at least one of the plurality of test operation signals, and then (iii) testing at least a portion of the IC device in response to the generating the test enable signal. The generating may also include generating a test enable signal in response to detecting, on the wafer, an inactive-to-active transition of a toggle detection signal.
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