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    THREE-DIMENSIONAL TRANSMON QUBIT APPARATUS
    2.
    发明申请
    THREE-DIMENSIONAL TRANSMON QUBIT APPARATUS 有权

    公开(公告)号：US20210216899A1

    公开(公告)日：2021-07-15

    申请号：US16916832

    申请日：2020-06-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehyeong LEE ,  Hyeokshin KWON ,  Insu JEON

    IPC: G06N10/00 ,  H01L27/18

    Abstract: Provided is a three-dimensional (3D) transmon qubit apparatus including a body portion, a driver, a transmon element disposed in an internal space of the body portion, a first tunable cavity module disposed in the internal space of the body, and comprising a first superconductive metal panel; and a second tunable cavity module disposed in the internal space of the body, and comprising a second superconductive metal panel, wherein the transmon element is disposed between the first superconductive metal panel and the second superconductive metal panel; wherein the first tunable cavity module and the second tunable cavity module are configured to adjust a distance between the first superconductive metal panel and the second superconductive metal panel, and wherein the driver is configured to tune a resonance frequency by adjusting a 3D cavity by adjusting the distance between the first superconductive metal panel and the second superconductive metal panel.

    Josephson Junction Device and Method of Manufacture Thereof
    3.
    发明申请
    Josephson Junction Device and Method of Manufacture Thereof 有权

    公开(公告)号：US20250169376A1

    公开(公告)日：2025-05-22

    申请号：US18664982

    申请日：2024-05-15

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jaehyeong LEE ,  Hyeokshin KWON ,  Daeyun KIM ,  Daeseok HAN

    IPC: H10N60/01 ,  H10N60/12 ,  H10N60/85

    Abstract: A Josephson junction device has a second region between first and third regions, and the Josephson junction device includes: a substrate in the first, second, and third regions; a first superconductive layer arranged on the substrate in the first and second regions and not the third region; a second superconductive layer arranged in the second and third regions and spatially overlapping the first superconductive layer in the second region; an oxide layer sandwiched between the first superconductive layer the second superconductive in the second region; and a first trench in the substrate in the third region, the trench passing under the second superconductive layer in the third region.

    QUANTUM COMPUTING DEVICE AND SYSTEM
    4.
    发明申请
    QUANTUM COMPUTING DEVICE AND SYSTEM 有权

    公开(公告)号：US20210328127A1

    公开(公告)日：2021-10-21

    申请号：US17227661

    申请日：2021-04-12

    Applicant: Samsung Electronics Co., Ltd

    Inventor： Hyeokshin KWON ,  Jaehyeong LEE ,  Insu JEON

    IPC: H01L39/22 ,  H01L39/02 ,  G06N10/00

    Abstract: Provided is a quantum computing device and system. The quantum computing device includes a first qubit chip, a readout cavity structure surrounding a first end part of the first qubit chip, and a storage cavity structure surrounding a second end part of the first qubit chip, wherein the first qubit chip includes a first readout antenna disposed within the readout cavity structure, a first storage antenna disposed in the storage cavity structure, and a first qubit element provided between the first readout antenna and the first storage antenna, and wherein the first qubit element is disposed between the readout cavity structure and the storage cavity structure.

    METHOD AND DEVICE WITH JOSEPHSON JUNCTION
    6.
    发明公开
    METHOD AND DEVICE WITH JOSEPHSON JUNCTION 审中-公开

    公开(公告)号：US20240260483A1

    公开(公告)日：2024-08-01

    申请号：US18507672

    申请日：2023-11-13

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Daeseok HAN ,  Jaehyeong LEE ,  Jinhyoun KANG ,  Daeyun KIM ,  Jaeho SHIN ,  Daeho YANG

    IPC: H10N60/12 ,  H10N60/01 ,  H10N60/80

    CPC classification number: H10N60/124 ,  H10N60/0941 ,  H10N60/805

    Abstract: A device including a Josephson junction device including a first superconductor layer, a first oxide layer disposed on a first upper surface of the first superconductor layer, a second superconductor layer disposed to partially overlap the first superconductor layer, a second oxide layer disposed on a second upper surface of the second superconductor layer, and a third superconductor layer including a first portion facing the first upper surface of the first superconductor layer and a second portion facing the second upper surface of the second superconductor layer, and a first thickness of a first portion of the first oxide layer between a lower surface of the first portion of the third superconductor layer and a third upper surface of the first superconductor layer is less than a second thickness of a second portion of the first oxide layer.

    QUBIT CHIP DEVICE AND METHOD OF MANUFACTURING THE SAME
    8.
    发明公开
    QUBIT CHIP DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240260487A1

    公开(公告)日：2024-08-01

    申请号：US18488645

    申请日：2023-10-17

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jaehyeong LEE ,  Jinhyoun KANG ,  Insu JEON ,  Jaeho SHIN

    IPC: H10N69/00

    CPC classification number: H10N69/00

    Abstract: A qubit chip device includes: a substrate; a superconducting qubit on the substrate; and a readout circuit on the substrate and electrically connected to the superconducting qubit, the readout circuit including: a signal line on a surface of the substrate; a ground plate on the surface of the substrate, the ground plate including a pattern forming a coplanar waveguide along the signal line and offset from the signal line; and a conductive bridge embedded in the substrate and connecting two portions of the ground plate in a direction crossing the signal line.

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