Abstract:
A thin film transistor array panel includes: a substrate, a gate line positioned on the substrate and including a gate electrode, a semiconductor layer positioned on the substrate and including an oxide semiconductor, a data wire layer positioned on the substrate and including a data line crossing the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode, and a capping layer covering the data wire layer, in which an end of the capping layer is inwardly recessed as compared to an end of the data wire layer.
Abstract:
A liquid crystal display includes a first substrate including a plurality of pixels, a second substrate facing the first substrate, and a liquid crystal layer interposed between the first substrate and the second substrate. At least one of the pixels includes a thin film transistor disposed on a first insulating substrate, an insulating layer overlapping the thin film transistor, and a pixel electrode disposed on the insulating layer. A contact hole is formed through the insulating layer to expose a first electrode of the thin film transistor, the pixel electrode is electrically connected to the first electrode through the contact hole, and the pixel electrode has a single-layer in an area where the contact hole is formed and a double-layer on the insulating layer.