公开(公告)号：US20240138188A1

公开(公告)日：2024-04-25

申请号：US18227610

申请日：2023-07-27

Applicant: Samsung Display Co., LTD.

Inventor： Hyun Joon KIM ,  Bon-Yong KOO ,  DANWON LIM ,  JAEYONG JANG

IPC: H10K59/121 ,  H10K59/131

CPC classification number: H10K59/1213 ,  H10K59/1216 ,  H10K59/131

Abstract: A light emitting display device includes: a driving transistor including a driving gate electrode, and first and second electrodes; a storage capacitor including first and second storage electrodes; a second transistor including electrodes connected to a data line and the second storage electrode, respectively; a third transistor including electrodes connected to the second electrode of the driving transistor and the driving gate electrode, respectively; a hold capacitor including first and second hold electrodes connected to a first driving voltage line and the second storage electrode, respectively; and a ninth transistor including electrodes connected to the first driving voltage line and the first electrode of the driving transistor, respectively. The second storage and hold electrodes are integrally formed, the driving gate electrode and the first storage electrode are integrally formed, and the driving gate electrode, the second storage electrode, and the first hold electrode overlap each other.

公开(公告)号：US20150194444A1

公开(公告)日：2015-07-09

申请号：US14274541

申请日：2014-05-09

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Dong Yeon SON

IPC: H01L27/12

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/124

Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.

Abstract translation: 提供了一种显示装置，更具体地，涉及包括栅极驱动器的显示装置。 显示装置包括：多个像素; 连接到所述多个像素的多个栅极线; 栅极驱动器，其包括多个级以向多条栅极线输出栅极信号; 将时钟信号传送到门驱动器的时钟信号线; 将栅极驱动器断开电压的电压布线; 其中时钟信号布线位于栅极驱动器的第一侧，并且电压布线位于面对栅极驱动器的第一侧的第二侧。

公开(公告)号：US20140312353A1

公开(公告)日：2014-10-23

申请号：US14322366

申请日：2014-07-02

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Jeong Min Park ,  Ho-Kyoon Kwon ,  Yun Hee Kwak

IPC: H01L27/12

CPC classification number: H01L27/1214 ,  G02F1/13458 ,  G02F1/136227 ,  H01L27/124

Abstract: A thin film transistor array panel includes a gate line and the driver connection line formed with the same layer material, a data line and a driving pad formed with the same layer material, a first field generating electrode and a connecting member formed with the same layer material, and a second field generating electrode and a dummy electrode layer formed with the same layer material.

Abstract translation: 薄膜晶体管阵列面板包括栅极线和形成有相同层材料的驱动器连接线，形成有相同层材料的数据线和驱动焊盘，第一场产生电极和形成有相同层的连接构件 材料和形成有相同层材料的第二场产生电极和虚拟电极层。

公开(公告)号：US20130277674A1

公开(公告)日：2013-10-24

申请号：US13918060

申请日：2013-06-14

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Kyung-Wook KIM

IPC: H01L21/66

CPC classification number: H01L27/105 ,  G02F1/1309 ,  G02F1/1345 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.

Abstract translation: 显示面板包括具有显示区域和周边区域的绝缘基板，布置在显示区域中的绝缘基板上的布线，布置在绝缘基板上并基本上彼此平行排列的第一和第二测试线，以及设置在二极管单元 在第一测试线和第二测试线之间。 电线从显示区域延伸到外围区域，并通过二极管单元中包含的二极管延伸，并且电线电连接到第一测试线和第二测试线之一。

公开(公告)号：US20140191238A1

公开(公告)日：2014-07-10

申请号：US14099977

申请日：2013-12-08

Applicant: Samsung Display Co., Ltd.

Inventor： Jung Hwan HWANG ,  Bon-Yong KOO ,  Soo Jin PARK ,  Jong-Moon PARK ,  Yong Hee LEE ,  Jong-Hyuk LEE ,  Duc-Han CHO

IPC: H01L27/12 ,  H01L27/15

CPC classification number: H01L29/41733 ,  H01L27/1214 ,  H01L27/124 ,  H01L27/156 ,  H01L29/41775

Abstract: A thin film transistor array panel includes a gate line elongated in an extension direction and including a gate and dummy gate electrode extended therefrom; and a source electrode, and a single drain member including a drain electrode at a first end thereof and a dummy drain electrode at an opposing second end thereof. The drain electrode faces the source electrode with respect to the gate electrode, and the dummy drain electrode overlaps the dummy gate electrode. The drain and dummy drain electrode respectively include a plurality of first and second regions each having a predetermined width in the extension direction. A second region includes an edge which forms an angle from about 0 degrees to about 90 degrees with the extension direction, and a planar area of at least one of the plurality of second regions is different from that of remaining second regions.

Abstract translation: 薄膜晶体管阵列面板包括在延伸方向上延伸的栅极线，并且包括从其延伸的栅极和虚拟栅电极; 源电极和在其第一端包括漏极的单个漏极构件和在其相对的第二端处的虚设漏电极。 漏电极相对于栅电极面对源电极，虚设漏电极与虚拟栅电极重叠。 漏极和虚设漏电极分别包括在延伸方向上具有预定宽度的多个第一和第二区域。 第二区域包括与延伸方向形成约0度至约90度的角度的边缘，并且多个第二区域中的至少一个的平面区域与剩余的第二区域的平面区域不同。

公开(公告)号：US20140084294A1

公开(公告)日：2014-03-27

申请号：US14092102

申请日：2013-11-27

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Kyung-Wook KIM

IPC: H01L27/105

CPC classification number: H01L27/105 ,  G02F1/1309 ,  G02F1/1345 ,  H01L22/32 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A display panel includes an insulation substrate having a display area and a peripheral area, wires disposed on the insulation substrate in the display area, first and second testing lines disposed on the insulation substrate and aligned substantially parallel to each other, and a diode unit disposed between the wires and one of the first testing line and the second testing line. The wires extend from the display area into the peripheral area and through diodes included in the diode unit, and the wires are electrically connected to the one of the first testing line and the second testing line.

Abstract translation: 显示面板包括具有显示区域和周边区域的绝缘基板，布置在显示区域中的绝缘基板上的布线，布置在绝缘基板上并基本上彼此平行排列的第一和第二测试线，以及设置在二极管单元 在第一测试线和第二测试线之间。 电线从显示区域延伸到外围区域，并通过二极管单元中包含的二极管延伸，并且电线电连接到第一测试线和第二测试线之一。

公开(公告)号：US20240237403A9

公开(公告)日：2024-07-11

申请号：US18227610

申请日：2023-07-28

Applicant: Samsung Display Co., LTD.

Inventor： Hyun Joon KIM ,  Bon-Yong KOO ,  DANWON LIM ,  JAEYONG JANG

IPC: H10K59/121 ,  H10K59/131

CPC classification number: H10K59/1213 ,  H10K59/1216 ,  H10K59/131

Abstract: A light emitting display device includes: a driving transistor including a driving gate electrode, and first and second electrodes; a storage capacitor including first and second storage electrodes; a second transistor including electrodes connected to a data line and the second storage electrode, respectively; a third transistor including electrodes connected to the second electrode of the driving transistor and the driving gate electrode, respectively; a hold capacitor including first and second hold electrodes connected to a first driving voltage line and the second storage electrode, respectively; and a ninth transistor including electrodes connected to the first driving voltage line and the first electrode of the driving transistor, respectively. The second storage and hold electrodes are integrally formed, the driving gate electrode and the first storage electrode are integrally formed, and the driving gate electrode, the second storage electrode, and the first hold electrode overlap each other.

公开(公告)号：US20230413625A1

公开(公告)日：2023-12-21

申请号：US18313805

申请日：2023-05-08

Applicant: Samsung Display Co., LTD.

Inventor： Bon-Yong KOO ,  SUJIN LEE ,  DANWON LIM ,  JAEYONG JANG

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: One or more embodiments of the present disclosure provides a display device in cluding: a substrate configured to include a display area including pixels and signal line s, and a peripheral area positioned around the display area; a semiconductor layer on t he substrate; a first conductive layer between the semiconductor layer and the substrat e; a second conductive layer positioned between the first conductive layer and the sem iconductor layer; a gate conductive layer on the semiconductor layer; and a third condu ctive layer on the gate conductive layer, wherein the peripheral area includes a fan-out portion in which fan-out wires connected to the signal lines are positioned, and the fan-out wires include a first fan-out wire, a second fan-out wire, and a third fan-out wire whi ch are alternately positioned in different ones among the first conductive layer, the sec and conductive layer, and the gate conductive layer.

公开(公告)号：US20220189399A1

公开(公告)日：2022-06-16

申请号：US17526483

申请日：2021-11-15

Applicant: Samsung Display Co., LTD.

Inventor： Ki Hyun PYO ,  Bon-Yong KOO ,  Ji-Sun KIM ,  Hyeong Seok KIM

IPC: G09G3/3233

Abstract: A display device includes a first pixel circuit, a first scan signal line disposed at a side of the first pixel circuit, extending in a first direction, and transmitting a scan signal; a second pixel circuit disposed at an outermost side of the display device, and a first dummy wire disposed at an outside of the second pixel circuit and extending in the first direction. A width of the first dummy wire is less than a width of the first scan signal line.

公开(公告)号：US20190325811A1

公开(公告)日：2019-10-24

申请号：US16502438

申请日：2019-07-03

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Dong Yeon SON

IPC: G09G3/20 ,  G09G3/36 ,  H01L27/12

Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver, in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.