公开(公告)号：US20160300545A1

公开(公告)日：2016-10-13

申请号：US14978338

申请日：2015-12-22

Applicant: Samsung Display Co., Ltd.

Inventor： Kyung Hee KIM ,  Yun Hee KWAK ,  Dong Yeon SON

IPC: G09G5/00 ,  G09G3/00

CPC classification number: G09G3/006 ,  G02F1/13452 ,  G09G3/20 ,  G09G2300/0408 ,  G09G2300/0426

Abstract: A display device including a display panel including a chip mounting region and a driver mounted on the chip mounting region, the driver configured to provide signals to a display region of the display device to display an image on the display region. The display panel includes a first connection line, a second connection wire line, and a third connection wire line sequentially disposed in the chip mounting region; a first shorting bar, a second shorting bar, and a third shorting bar correspondingly connected to the first connection wire line, the second connection wire line, and the third connection wire line; and a bridge wire line configured to electrically connect at least one of the first, second, and third shorting bars and the second connection wire line. Neighboring connection wire lines of the first, second, and third connection wire lines are disposed in different layers.

Abstract translation: 一种显示装置，包括具有芯片安装区域的显示面板和安装在芯片安装区域上的驱动器，所述驱动器被配置为向显示装置的显示区域提供信号，以在显示区域上显示图像。 所述显示面板包括顺序地配置在所述芯片安装区域中的第一连接线，第二连接线线和第三连接线线路; 相应地连接到第一连接线，第二连接线和第三连接线的第一短路棒，第二短路棒和第三短接棒; 以及桥电线，其被配置为电连接所述第一，第二和第三短路棒和所述第二连接线线中的至少一个。 第一，第二和第三连接线的相邻连接线线设置在不同的层中。

公开(公告)号：US20150194444A1

公开(公告)日：2015-07-09

申请号：US14274541

申请日：2014-05-09

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Dong Yeon SON

IPC: H01L27/12

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/124

Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.

Abstract translation: 提供了一种显示装置，更具体地，涉及包括栅极驱动器的显示装置。 显示装置包括：多个像素; 连接到所述多个像素的多个栅极线; 栅极驱动器，其包括多个级以向多条栅极线输出栅极信号; 将时钟信号传送到门驱动器的时钟信号线; 将栅极驱动器断开电压的电压布线; 其中时钟信号布线位于栅极驱动器的第一侧，并且电压布线位于面对栅极驱动器的第一侧的第二侧。

公开(公告)号：US20150205154A1

公开(公告)日：2015-07-23

申请号：US14456119

申请日：2014-08-11

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Dong Yeon SON

IPC: G02F1/1345 ,  G02F1/1368 ,  G02F1/1333 ,  G02F1/1362

CPC classification number: G02F1/1345 ,  G02F1/13454 ,  G09G3/36 ,  G09G3/3648 ,  G09G2300/0408

Abstract: A display device is provided. A display device according to an exemplary embodiment of the present invention includes a display panel including: a display area where a plurality of pixels are disposed and a peripheral area near the display area; and a gate driver disposed in the peripheral area and including a transistor unit and a common voltage application unit, wherein the common voltage application unit overlaps via a first insulating layer disposed on the transistor unit.

Abstract translation: 提供显示装置。 根据本发明的示例性实施例的显示装置包括：显示面板，包括：多个像素的显示区域和显示区域附近的周边区域; 以及设置在所述周边区域中并包括晶体管单元和公共电压施加单元的栅极驱动器，其中所述公共电压施加单元经由设置在所述晶体管单元上的第一绝缘层重叠。

公开(公告)号：US20150194112A1

公开(公告)日：2015-07-09

申请号：US14262414

申请日：2014-04-25

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Dong Yeon SON

IPC: G09G3/36

CPC classification number: G09G3/3648 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286

Abstract: The output stage of a monolithically integrated gate lines driver circuit of a display device has a capacitor boosted, source-follower configuration in which a relatively large area transistor (Tr1) receives drive power at its drain from a clock signal providing rail (CK), a source of the transistor drives a respective gate line and a relatively large area boost capacitor (C1) connects to gate and the source of the transistor. In order to reduce consumption of substrate area, the relatively large area boost capacitor is laid out to overlap the transistor while a relatively thick first insulating layer of relatively low dielectric constant positioned between the transistor and the overlying boost capacitor.

Abstract translation: 显示装置的单片集成栅线驱动电路的输出级具有电容升压的源极跟随器配置，其中较大面积的晶体管（Tr1）从时钟信号提供轨（CK）在其漏极接收驱动功率， 晶体管的源极驱动相应的栅极线，并且相对较大的区域升压电容器（C1）连接到晶体管的栅极和源极。 为了减少衬底面积的消耗，相对较大的面积升压电容器布置成与晶体管重叠，而位于晶体管和上覆升压电容器之间的相对较薄介电常数相对较厚的第一绝缘层。

公开(公告)号：US20190325811A1

公开(公告)日：2019-10-24

申请号：US16502438

申请日：2019-07-03

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Dong Yeon SON

IPC: G09G3/20 ,  G09G3/36 ,  H01L27/12

Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver, in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.

公开(公告)号：US20170206827A1

公开(公告)日：2017-07-20

申请号：US15476213

申请日：2017-03-31

Applicant: Samsung Display Co., Ltd.

Inventor： Bon-Yong KOO ,  Dong Yeon SON

IPC: G09G3/20 ,  H01L27/12

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/124

Abstract: Provided is a display device, more particularly, a display device including a gate driver. The display device includes: a plurality of pixels; a plurality of gate lines connected to the plurality of pixels; a gate driver including a plurality of stages outputting gate signals to the plurality of gate lines; a clock signal wiring transferring a clock signal to the gate driver; a voltage wiring transferring an off voltage to the gate driver; in which the clock signal wiring is positioned at a first side of the gate driver, and the voltage wiring is positioned at a second side facing the first side of the gate driver.