LIGHT EMITTING DISPLAY DEVICE
    2.
    发明公开

    公开(公告)号:US20240138188A1

    公开(公告)日:2024-04-25

    申请号:US18227610

    申请日:2023-07-27

    CPC classification number: H10K59/1213 H10K59/1216 H10K59/131

    Abstract: A light emitting display device includes: a driving transistor including a driving gate electrode, and first and second electrodes; a storage capacitor including first and second storage electrodes; a second transistor including electrodes connected to a data line and the second storage electrode, respectively; a third transistor including electrodes connected to the second electrode of the driving transistor and the driving gate electrode, respectively; a hold capacitor including first and second hold electrodes connected to a first driving voltage line and the second storage electrode, respectively; and a ninth transistor including electrodes connected to the first driving voltage line and the first electrode of the driving transistor, respectively. The second storage and hold electrodes are integrally formed, the driving gate electrode and the first storage electrode are integrally formed, and the driving gate electrode, the second storage electrode, and the first hold electrode overlap each other.

    LIGHT EMITTING DISPLAY DEVICE
    3.
    发明公开

    公开(公告)号:US20240237403A9

    公开(公告)日:2024-07-11

    申请号:US18227610

    申请日:2023-07-28

    CPC classification number: H10K59/1213 H10K59/1216 H10K59/131

    Abstract: A light emitting display device includes: a driving transistor including a driving gate electrode, and first and second electrodes; a storage capacitor including first and second storage electrodes; a second transistor including electrodes connected to a data line and the second storage electrode, respectively; a third transistor including electrodes connected to the second electrode of the driving transistor and the driving gate electrode, respectively; a hold capacitor including first and second hold electrodes connected to a first driving voltage line and the second storage electrode, respectively; and a ninth transistor including electrodes connected to the first driving voltage line and the first electrode of the driving transistor, respectively. The second storage and hold electrodes are integrally formed, the driving gate electrode and the first storage electrode are integrally formed, and the driving gate electrode, the second storage electrode, and the first hold electrode overlap each other.

    DISPLAY DEVICE
    4.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20240096281A1

    公开(公告)日:2024-03-21

    申请号:US18321900

    申请日:2023-05-23

    Abstract: A display device includes a display panel including a first pixel, a second pixel, and a connection line connecting the first pixel and the second pixel. Each of the first pixel and the second pixel includes a light emitting element, a first transistor including a first electrode, a second electrode electrically connected to the light emitting element, and a gate electrode, a second transistor connected between a first driving voltage line and a connection node and including a gate electrode connected to an emission line, a third transistor connected between a second driving voltage line and the connection node and including a gate electrode connected to the emission line, and a capacitor connected between the gate electrode of the first transistor and the connection node. The connection node of the first pixel is electrically connected to the connection node of the second pixel through the connection line.

    DISPLAY DEVICE
    5.
    发明公开
    DISPLAY DEVICE 审中-公开

    公开(公告)号:US20230413625A1

    公开(公告)日:2023-12-21

    申请号:US18313805

    申请日:2023-05-08

    CPC classification number: H10K59/131

    Abstract: One or more embodiments of the present disclosure provides a display device in cluding: a substrate configured to include a display area including pixels and signal line s, and a peripheral area positioned around the display area; a semiconductor layer on t he substrate; a first conductive layer between the semiconductor layer and the substrat e; a second conductive layer positioned between the first conductive layer and the sem iconductor layer; a gate conductive layer on the semiconductor layer; and a third condu ctive layer on the gate conductive layer, wherein the peripheral area includes a fan-out portion in which fan-out wires connected to the signal lines are positioned, and the fan-out wires include a first fan-out wire, a second fan-out wire, and a third fan-out wire whi ch are alternately positioned in different ones among the first conductive layer, the sec and conductive layer, and the gate conductive layer.

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