Gate driver and display device having the same

    公开(公告)号:US12283223B2

    公开(公告)日:2025-04-22

    申请号:US18125135

    申请日:2023-03-23

    Abstract: Provided is a gate driver comprising an inverter inverting a start signal to generate an inverted start signal, a first driver including a first stage generating a bias gate signal to initialize a light emitting element of each of pixels in response to the inverted start signal, and a second driver including a second stage generating a write gate signal to apply data voltages to the pixels in response to the start signal. Accordingly, the gate driver may generate a plurality of gate signals using one start signal. In addition, since the gate driver generates a write gate signal and a bias gate signal using one start signal, a bias operation and a light emitting element initialization operation may be performed in a self-scan period without adding the start signal. Further, a size of the gate driver may be reduced, and accordingly, the gate driver may be efficiently disposed.

    Liquid crystal display
    8.
    发明授权
    Liquid crystal display 有权
    液晶显示器

    公开(公告)号:US09052553B2

    公开(公告)日:2015-06-09

    申请号:US13837861

    申请日:2013-03-15

    Abstract: A liquid crystal display includes a first substrate, a first gate line disposed on the first substrate, a second gate line disposed on the first substrate, a data line disposed on the first substrate, a reference voltage line disposed on the first substrate and extending substantially to be parallel to the data line, a first subpixel electrode disposed in a pixel area on the first substrate, a second subpixel electrode disposed in the pixel area on the first substrate, a first switching element connected to the first gate line, the data line and the first subpixel electrode, a second switching element connected to the first gate line, the data line and the second subpixel electrode, and a third switching element connected to the first subpixel electrode and the reference voltage line.

    Abstract translation: 液晶显示器包括第一基板,设置在第一基板上的第一栅极线,设置在第一基板上的第二栅极线,设置在第一基板上的数据线,设置在第一基板上的基准电压线, 平行于数据线,设置在第一基板上的像素区域中的第一子像素电极,设置在第一基板上的像素区域中的第二子像素电极,连接到第一栅极线的第一开关元件,数据线 第一子像素电极,与第一栅极线连接的第二开关元件,数据线和第二子像素电极,以及与第一子像素电极和基准电压线连接的第三开关元件。

    Inverter circuit, scan driving circuit and display device

    公开(公告)号:US12106707B2

    公开(公告)日:2024-10-01

    申请号:US18342833

    申请日:2023-06-28

    CPC classification number: G09G3/32 G09G2310/0267 G09G2310/0275

    Abstract: An inverter circuit in a scan driving circuit of a display device that includes an output transistor connected between a first voltage line and an output terminal outputting a second start signal and including a gate electrode connected to an input terminal receiving a first start signal, a first switching transistor connected between the first voltage line and the output terminal and including a gate electrode connected to a first switching line receiving a first switching signal, a second switching transistor connected between the output terminal and a first node and including a gate electrode connected to a second switching line receiving a second switching signal, and a discharge circuit that discharges the first node to a first bias clock signal in response to the first start signal, the first bias clock signal, and a second bias clock signal.

    Display device
    10.
    发明授权

    公开(公告)号:US10578940B2

    公开(公告)日:2020-03-03

    申请号:US15852375

    申请日:2017-12-22

    Abstract: A display device includes: a display panel in which a plurality of pixels are arranged; a plurality of gate lines disposed in the display panel and transmitting a gate signal to the plurality of pixels; a gate driver disposed in the display panel and including a plurality of stages for generating the gate signal and outputting the gate signal to the plurality of gate lines; and a plurality of clock signal lines disposed in the display panel and transmitting a clock signal to the plurality of stages. Each stage of the plurality of stages includes a clock signal terminal connected to one of the plurality of clock signal lines to receive the clock signal, a first output terminal connected to a corresponding gate line to output the gate signal, and a first transistor and a second transistor connected to the first output terminal. The stages have a substantially same area, and a size of the second transistor of a first stage disposed at an upper portion of the display panel is different from a size of the second transistor of a second stage disposed at a lower portion of the display panel.

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