Abstract:
A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.
Abstract:
A display device includes a display panel, a controller, a power supplier, and an initialization voltage generator. The controller generates a power control signal based on an input image. The power supplier generates a variable driving voltage that is changed based on the power control signal. The initialization voltage generator changes an initialization voltage to initialize the pixels based on the variable driving voltage.
Abstract:
A display apparatus includes a timing controller, a data driver and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of an input image. The timing controller generates a data signal having the first frequency based on the input image data having the first frequency. The data driver converts the data signal into a data voltage. The display panel displays an image based on the data voltage.
Abstract:
A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.
Abstract:
A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.
Abstract:
A display device includes a display panel including a plurality of pixels, a scan driving unit configured to provide a scan signal to the pixels, a data driving unit configured to provide a data signal to the pixels, and a controller configured to provide driving frequency information to a processor, which transfers image data with a driving frequency determined based on the driving frequency information to the display device, to receive the image data with the driving frequency from the processor, and to control the scan driving unit and the data driving unit to drive the display panel with the driving frequency.
Abstract:
A display apparatus includes a timing controller, a data driver and a display panel. The timing controller receives input image data at a first frequency substantially equal to a frame rate of an input image. The timing controller generates a data signal having the first frequency based on the input image data having the first frequency. The data driver converts the data signal into a data voltage. The display panel displays an image based on the data voltage.
Abstract:
A gate driver includes stages configured to output gate signals and gate initialization signals. Here, an Nth stage includes a first output block configured to generate an Nth carry signal based on an N−1th carry signal and to generate an Nth gate initialization signal based on the N−1th carry signal, an output enable signal, and an output disable signal that is an inverted signal of the output enable signal; and a second output block configured to generate an Nth gate signal by shifting the Nth gate initialization signal by a horizontal time, where N is a positive integer.
Abstract:
A stage of a gate driver includes a carry generate block configured to output an (N)-th carry signal based on an input signal and to provide the (N)-th carry signal to an (N+1)-th stage; a first output block configured to output an (N)-th gate initialization signal based on the input signal, an input enable signal, and an input disable signal, wherein the input disable signal is inverted with respect to the input enable signal; and a second output block configured to receive the (N)-th gate initialization signal and to output an (N)-th gate signal according to the output of the (N)-th gate initialization signal; the (N)-th gate signal being delayed one horizontal period from the (N)-th gate initialization signal, wherein the gate signals and the gate initialization signals of the stages are selectively output based on the input enable signal and the input disable signal.
Abstract:
A display apparatus includes an image analyzer that analyzes image data and outputs an interrupt signal at a period during which the image data of a low frequency change to the image data of a high frequency, a frequency detector that detects the high frequency, a frame rate controller that outputs a vertical synch signal of the high frequency in response to the interrupt signal, a polarity compensation controller that determines a last frame of the low frequency based on an interrupt period at which the interrupt signal is generated, generates a reversed polarity signal with respect to a polarity signal of the last frame and outputs the reversed polarity signal during a polarity compensation period close to the interrupt period, and a data driver circuit that outputs a data signal based on the reversed polarity signal to a data line during the polarity compensation period.