Reset circuitry for mitigating offsets in a MEMS device interpolator
    1.
    发明授权
    Reset circuitry for mitigating offsets in a MEMS device interpolator 有权
    用于减轻MEMS器件内插器偏移的复位电路

    公开(公告)号:US09553571B1

    公开(公告)日:2017-01-24

    申请号:US14947886

    申请日:2015-11-20

    Inventor: Eugenio Miluzzi

    CPC classification number: H03K5/135 H03K2005/00052

    Abstract: A method and apparatus for mitigating offsets in an interpolator are disclosed. In the method and apparatus, a first number of clock cycles of a first clock signal observed over a first clock cycle of a second clock signal is determined and then stored. Also a second number of clock cycles of the first clock signal observed over a second clock cycle of the second clock signal subsequent to the first clock cycle is determined and stored. The first number of clock cycles and the second number of clock cycles are compared to determine whether they are different from each other. If they are different from each other, a reset signal is asserted under control of the second clock signal to reset at least one of a derivator stage and an integrator stage of an interpolator.

    Abstract translation: 公开了一种用于减轻内插器中的偏移的方法和装置。 在该方法和装置中,确定在第二时钟信号的第一时钟周期上观察到的第一时钟信号的第一数量的时钟周期,然后被存储。 还确定并存储在第一时钟周期之后的第二时钟信号的第二时钟周期上观察到的第一时钟信号的第二数量的时钟周期。 比较第一个时钟周期数和第二个时钟周期数,以确定它们是否彼此不同。 如果它们彼此不同,则在第二时钟信号的控制下确定复位信号以复位内插器的导数级和积分级中的至少一个。

    Dynamic definition of slave address in I2C protocol

    公开(公告)号:US10204066B2

    公开(公告)日:2019-02-12

    申请号:US15363932

    申请日:2016-11-29

    Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.

    Dynamic definition of slave address in I2C protocol

    公开(公告)号:US10459862B2

    公开(公告)日:2019-10-29

    申请号:US16219803

    申请日:2018-12-13

    Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.

    DYNAMIC DEFINITION OF SLAVE ADDRESS IN I2C PROTOCOL

    公开(公告)号:US20180150424A1

    公开(公告)日:2018-05-31

    申请号:US15363932

    申请日:2016-11-29

    CPC classification number: G06F13/364 G06F13/404 G06F13/4282

    Abstract: A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.

    Offset calibration in a multiple membrane microphone
    8.
    发明授权
    Offset calibration in a multiple membrane microphone 有权
    多重麦克风中的偏移校准

    公开(公告)号:US09560455B2

    公开(公告)日:2017-01-31

    申请号:US14752475

    申请日:2015-06-26

    Inventor: Eugenio Miluzzi

    Abstract: A multi-membrane microphone including an audio processing circuit is disclosed. The membranes are configured to output to a plurality of amplifiers a plurality of sensing signals in response to sound. The amplifiers in turn create amplified signals by amplifying the sensing signals and introduce a plurality of offsets into the amplified signals, respectively. The audio processing circuit includes a controller that sequentially measures the offset for each amplifier a corresponding membrane is inactive and stores the offset. The controller also compensates each amplified signal by the corresponding offset during operation of the multi-membrane microphone.

    Abstract translation: 公开了一种包括音频处理电路的多膜麦克风。 膜被配置为响应于声音向多个放大器输出多个感测信号。 放大器又通过放大感测信号并将多个偏移分别引入放大信号来产生放大信号。 音频处理电路包括一个控制器,该控制器顺序地测量每个放大器的偏移,相应的膜不活动并存储偏移。 控制器还在多膜麦克风的操作期间通过相应的偏移来补偿每个放大的信号。

    Circuit and method for dynamic offset compensation in a MEMS sensor device
    9.
    发明授权
    Circuit and method for dynamic offset compensation in a MEMS sensor device 有权
    MEMS传感器装置中动态偏移补偿的电路和方法

    公开(公告)号:US08981834B2

    公开(公告)日:2015-03-17

    申请号:US14134972

    申请日:2013-12-19

    CPC classification number: G05F1/625 G01D5/2448 G01P15/125

    Abstract: An offset-compensation circuit in a MEMS sensor device, provided with a micromechanical detection structure that transduces a quantity to be detected into an electrical detection quantity, and with an electronic reading circuit, coupled to the micromechanical detection structure for processing the electrical detection quantity and supplying an output signal, which is a function of the quantity to be detected. A compensation structure is electrically coupled to the input of the electronic reading circuit and can be controlled for generating an electrical compensation quantity, of a trimmable value, for compensating an offset on the output signal; the compensation circuit has a control unit, which reads the output signal during operation of the MEMS sensor device; obtains information on the offset present on the output signal itself; and controls the compensation structure as a function of the offset information.

    Abstract translation: MEMS传感器装置中的偏移补偿电路,其具有将要检测的量转换为电检测量的微机械检测结构,以及耦合到微机械检测结构的电子读取电路,用于处理电检测量;以及 提供作为要检测的量的函数的输出信号。 补偿结构电耦合到电子阅读电路的输入,并且可以被控制以产生可修整值的电补偿量,用于补偿输出信号上的偏移; 补偿电路具有控制单元,其在MEMS传感器设备的操作期间读取输出信号; 获取关于输出信号本身的偏移量的信息; 并且将补偿结构控制为偏移信息的函数。

    CIRCUIT AND METHOD FOR DYNAMIC OFFSET COMPENSATION IN A MEMS SENSOR DEVICE
    10.
    发明申请
    CIRCUIT AND METHOD FOR DYNAMIC OFFSET COMPENSATION IN A MEMS SENSOR DEVICE 有权
    用于MEMS传感器装置中的动态偏移补偿的电路和方法

    公开(公告)号:US20140176231A1

    公开(公告)日:2014-06-26

    申请号:US14134972

    申请日:2013-12-19

    CPC classification number: G05F1/625 G01D5/2448 G01P15/125

    Abstract: An offset-compensation circuit in a MEMS sensor device, provided with a micromechanical detection structure that transduces a quantity to be detected into an electrical detection quantity, and with an electronic reading circuit, coupled to the micromechanical detection structure for processing the electrical detection quantity and supplying an output signal, which is a function of the quantity to be detected. A compensation structure is electrically coupled to the input of the electronic reading circuit and can be controlled for generating an electrical compensation quantity, of a trimmable value, for compensating an offset on the output signal; the compensation circuit has a control unit, which reads the output signal during operation of the MEMS sensor device; obtains information on the offset present on the output signal itself; and controls the compensation structure as a function of the offset information.

    Abstract translation: MEMS传感器装置中的偏移补偿电路,其具有将要检测的量转换为电检测量的微机械检测结构,以及耦合到微机械检测结构的电子读取电路,用于处理电检测量;以及 提供作为要检测的量的函数的输出信号。 补偿结构电耦合到电子阅读电路的输入,并且可以被控制以产生可修整值的电补偿量,用于补偿输出信号上的偏移; 补偿电路具有控制单元,其在MEMS传感器设备的操作期间读取输出信号; 获取关于输出信号本身的偏移量的信息; 并且将补偿结构控制为偏移信息的函数。

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