公开(公告)号：US20220302041A1

公开(公告)日：2022-09-22

申请号：US17469952

申请日：2021-09-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWANYONG KIM ,  SUNGWON SHIN ,  SEUNGMIN LEE ,  JUYOUNG LIM ,  WONSEOK CHO

IPC: H01L23/532 ,  H01L23/528 ,  H01L27/11539

Abstract: A semiconductor device includes a first stack structure on a substrate, and a second stack structure on the first stack structure. A channel structure extends through the first stack structure and the second stack structure. A first auxiliary stack structure including a plurality of first insulating layers and a plurality of first mold layers are alternately stacked on the substrate. An alignment key extends into the first auxiliary stack structure and protrudes to a higher level than an uppermost end of the first stack structure. A second auxiliary stack structure is disposed on the first auxiliary stack structure and the alignment key, and includes a plurality of second insulating layers and a plurality of second mold layers alternately stacked. The second auxiliary stack structure includes a protrusion aligned with the alignment key.

公开(公告)号：US20230354604A1

公开(公告)日：2023-11-02

申请号：US18072312

申请日：2022-11-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEUNGMIN LEE ,  JUNHYOUNG KIM ,  YOUNGBUM WOO ,  JOONSUNG LIM

IPC: H10B43/27 ,  H10B41/10 ,  H01L23/522 ,  H01L23/528 ,  H10B41/35 ,  H10B41/27 ,  H10B43/35 ,  H10B43/10

CPC classification number: H01L27/11582 ,  H01L27/11519 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11565

Abstract: A semiconductor device includes a first semiconductor structure including a first substrate, circuit devices disposed on the first substrate, and first metal bonding layers disposed on the circuit devices, and a second semiconductor structure including gate electrodes spaced apart from each other and stacked in a first direction, perpendicular to upper surfaces of the first metal bonding layers, channel structures passing through the gate electrodes, extending in the first direction, and respectively including a channel layer, second metal bonding layers disposed below the channel structures and the gate electrodes and connected to the first metal bonding layers, bit lines disposed below the channel structures, extending in a second direction, perpendicular to the first direction, and spaced apart from each other, and source lines disposed on the channel structures, extending in a third direction, perpendicular to the second direction, and spaced apart from each other. The channel structures are respectively disposed in intersection regions in which the bit lines and the source lines intersect each other.

公开(公告)号：US20210305271A1

公开(公告)日：2021-09-30

申请号：US17032128

申请日：2020-09-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  JISUNG CHEON ,  YOONHWAN SON ,  SEUNGMIN LEE

IPC: H01L27/11578 ,  H01L27/11573 ,  H01L27/11568

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US20220415919A1

公开(公告)日：2022-12-29

申请号：US17897255

申请日：2022-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYOUNG KIM ,  JISUNG CHEON ,  YOONHWAN SON ,  SEUNGMIN LEE

IPC: H01L27/11578 ,  H01L27/11568 ,  H01L27/11573

Abstract: A semiconductor device includes a lower structure; a first upper structure including lower gate layers on the lower structure; a second upper structure including upper gate layers on the first upper structure; separation structures penetrating the first and second upper structures on the lower structure; a memory vertical structure penetrating the lower and upper gate layers between the separation structures; and a first contact plug penetrating the first and second upper structures and spaced apart from the lower and upper gate layers. Each of the first contact plug and the memory vertical structure includes a lateral surface having a bent portion. The bent portion of the lateral surface is disposed between a first height level on which an uppermost gate layer of the lower gate layers is disposed and a second height level on which a lowermost gate layer of the upper gate layers is disposed.

公开(公告)号：US20220415450A1

公开(公告)日：2022-12-29

申请号：US17850722

申请日：2022-06-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： THANH CUONG NGUYEN ,  DAEKEON KIM ,  JIYOUNG PARK ,  HYUNWOO KIM ,  SEUNGMIN LEE ,  INKOOK JANG ,  SUKKOO HONG

IPC: G16C20/30 ,  G16C20/70

Abstract: A method of estimating solubility includes obtaining input data representing a chemical structure of a target material; generating at least one descriptor based on the input data; obtaining at least one solubility parameter by providing the at least one descriptor to a machine learning model trained based on chemical structures and sample solubility parameters of sample materials; and calculating the solubility based on the at least one solubility parameter, wherein the at least one descriptor includes at least one of a zero-dimensional descriptor, a one-dimensional descriptor, a two-dimensional descriptor, or a three-dimensional descriptor, each representing the chemical structure of the target material.