公开(公告)号：US20190303282A1

公开(公告)日：2019-10-03

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong KIM ,  Jiseok KANG ,  Tae-Kyeong KO ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Wonjae SHIN ,  Yongjun YU ,  Insu CHOI

IPC: G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G11C11/56

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.

公开(公告)号：US20240321338A1

公开(公告)日：2024-09-26

申请号：US18529283

申请日：2023-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kideok HAN ,  Ki-Seok PARK ,  Young-Hoon SON ,  Do-Han KIM ,  Min-Su BAE ,  Yoenhwa LEE ,  Insu CHOI

IPC: G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G11C11/4096

Abstract: A training method of a memory device adjusting an eye window of a data signal in response to a duty cycle adjuster (DCA) includes performing a first training operation that selects a first DCA code corresponding to a first internal clock signal having a phase difference of 180° relative to a reference internal clock signal, and performing a second training operation that selects a second DCA code and a third DCA code respectively corresponding to a second internal clock signal and a third internal clock signal having a phase difference of 90° and 270° relative to reference internal clock signal. In the first training operation, the eye window size of the data signal is measured in units of two unit intervals, and in the second training operation, the eye window size of the data signal is measured in units of one unit interval.

公开(公告)号：US20230112776A1

公开(公告)日：2023-04-13

申请号：US17889117

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jeong KIM ,  Tae-Kyeong KO ,  Nam Hyung KIM ,  Do-Han KIM ,  Deokho SEO ,  Ho-Young LEE ,  Insu CHOI

IPC: G06F3/06

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

公开(公告)号：US20240160732A1

公开(公告)日：2024-05-16

申请号：US18504430

申请日：2023-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngjae PARK ,  Seungki HONG ,  Hyunbo KIM ,  Insu CHOI

IPC: G06F21/55

CPC classification number: G06F21/554 ,  G06F2221/034

Abstract: Provided is a memory device including a memory cell array including a plurality of memory cell rows, the plurality of memory cell rows being grouped into a plurality of segments, a row decoder connected to the plurality of memory cell rows, and a refresh control circuit configured to generate a refresh control signal for controlling a refresh operation on the plurality of memory cell rows.

公开(公告)号：US20220246200A1

公开(公告)日：2022-08-04

申请号：US17474666

申请日：2021-09-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu KIM ,  Namhyung KIM ,  Daejeong KIM ,  Dohan KIM ,  Chanik PARK ,  Deokho SEO ,  Wonjae SHIN ,  Changmin LEE ,  Ilguy JUNG ,  Insu CHOI

IPC: G11C11/406

Abstract: Provided are a memory device skipping a refresh operation and an operating method thereof. The memory device includes a memory cell array including N rows; a refresh controller configured to control a refresh operation for the N rows of the memory cell array based on a refresh command; and an access information storage circuit including a plurality of registers configured to store flag information corresponding to each of the N rows, wherein a first value indicates rows that have been accessed, and a second value indicates rows that have not been accessed. The refresh controller is further configured to control whether the refresh operation is performed for a first row of the N rows at a refresh timing for the first row based on the flag information corresponding to the first row

公开(公告)号：US20170308328A1

公开(公告)日：2017-10-26

申请号：US15492436

申请日：2017-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Young LIM ,  Ki-Seok OH ,  Sungyong SEO ,  Youngjin CHO ,  Insu CHOI

IPC: G06F3/06 ,  G11C11/406

Abstract: A method for operating a storage device includes sending a request for a internal operation time for an internal operation to an external device, receiving an internal operation command corresponding to the request from the external device, and performing the internal operation during the internal operation time based on the internal operation command.

公开(公告)号：US20250165685A1

公开(公告)日：2025-05-22

申请号：US18952627

申请日：2024-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongnoh KIM ,  Suhyun CHAE ,  Dohan KIM ,  Younghoon SON ,  Jeeyong LEE ,  Insu CHOI

IPC: G06F30/32 ,  G06N3/12

Abstract: An electronic device includes a Plackett-Burman design (PBD) execution circuit, a genetic algorithm (GA) execution circuit, and a control circuit. The PBD execution circuit is configured to generate an initial design of experiment (DOE) set including a plurality of initial cases regarding semiconductor characteristics of a memory device of an external device. The GA execution circuit is configured to convert a previous generation DOE set to a next generation DOE set. The control circuit is configured to transmit the initial DOE set to the external device, receive, from the external device, an initial characteristic evaluation, generate a starting DOE set based on the initial characteristic evaluation, and control a genetic algorithm to be performed with an experimental result of the starting DOE set as an input. Each of the plurality of initial cases corresponds to a combination of a plurality of setting values influencing the semiconductor characteristics.

公开(公告)号：US20240404570A1

公开(公告)日：2024-12-05

申请号：US18581187

申请日：2024-02-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ki-Seok PARK ,  Do-Han KIM ,  Minsu BAE ,  Chang-Hyun BAE ,  Young-Hoon SON ,  Hye-Seung YU ,  Yoenhwa LEE ,  Daihyun LIM ,  Insu CHOI ,  Kideok HAN

IPC: G11C7/22 ,  G11C7/10

Abstract: A method of training a memory device is provided. In first to third DCA training steps, a score for each of first to third DCA code combinations is calculated based on an eye window size of a data signal, and in response to a tie occurring among scores, a DCA code combination is selected based on the sum of an even-eye window minimum value and an odd-eye window minimum value of the data signal.

公开(公告)号：US20240004757A1

公开(公告)日：2024-01-04

申请号：US18295457

申请日：2023-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-Young LEE ,  Sung-Joon KIM ,  IIho KIM ,  Kyungjin PARK ,  Changho YUN ,  Jinhun JEONG ,  Insu CHOI ,  Kyung-Hee HAN ,  Yukyoung KIM ,  Jinwoo KIM ,  Chaeeun LEE ,  Yunmi HWANG

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/0793

Abstract: Disclosed is an electronic device including a memory module that includes at least one dynamic random access memory, and a processor configured to access the memory module, determine a corrected error count associated with an address of a corrected error in response to the corrected error being detected when data are read from the memory module, read an error log associated with the corrected error, determine a risk level of the corrected error based on the error log, and schedule a post package repair (PPR) for the address of the corrected error in response to the risk level of the corrected error being high.