公开(公告)号：US20210192248A1

公开(公告)日：2021-06-24

申请号：US17188166

申请日：2021-03-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chol-Min KIM ,  Tae-Kyeong KO ,  Ji-Yong LEE ,  Deok-Ho SEO

IPC: G06K9/00 ,  G06K9/62 ,  G06T1/20 ,  G06N3/08 ,  G06T1/60

Abstract: An electronic device includes a graphic processor and a memory device. The graphic processor includes an artificial neural network engine that makes an object recognition model learn by using learning data and weights to provide a learned object recognition model. The memory device divides a feature vector into a first sub feature vector and a second feature vector, and performs a first calculation to apply the second sub feature vector and the weights to the learned object recognition model to provide a second object recognition result. The artificial neural network engine performs a second calculation to apply the first sub feature vector and the weights to the learned object recognition model to provide a first object recognition result and provides the first object recognition result to the memory device. The second calculation is performed in parallel with the first calculation.

公开(公告)号：US20200074202A1

公开(公告)日：2020-03-05

申请号：US16295526

申请日：2019-03-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chol-Min KIM ,  Tae-Kyeong KO ,  Ji-Yong LEE ,  Deok-Ho SEO

IPC: G06K9/00 ,  G06K9/62 ,  G06T1/20 ,  G06T1/60 ,  G06N3/08

Abstract: An electronic device includes a graphic processor and a memory device. The graphic processor includes an artificial neural network engine that makes an object recognition model learn by using learning data and weights to provide a learned object recognition model. The memory device, divides a feature vector into a first sub feature vector and a second feature vector, and performs a first calculation to apply the second sub feature vector and the weights to the learned object recognition model to provide a second object recognition result. The artificial neural network engine performs a second calculation to apply the first sub feature vector and the weights to the learned object recognition model to provide a first object recognition result and provides the first object recognition result to the memory device. The second calculation is performed in parallel with the first calculation.

公开(公告)号：US20230112776A1

公开(公告)日：2023-04-13

申请号：US17889117

申请日：2022-08-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jeong KIM ,  Tae-Kyeong KO ,  Nam Hyung KIM ,  Do-Han KIM ,  Deokho SEO ,  Ho-Young LEE ,  Insu CHOI

IPC: G06F3/06

Abstract: An operation method of a memory controller, which is configured to control a memory module including a plurality of memory devices and at least one error correction code (ECC) device, is provided. The method includes reading a data set including user data stored in the plurality of memory devices and ECC data stored in the at least one ECC device, based on a read command and a first address, and writing uncorrectable data in a memory area, which is included in each of the plurality of memory devices and the at least one ECC device and corresponds to the first address, when an error of the user data is not corrected based on the ECC data.

公开(公告)号：US20130268721A1

公开(公告)日：2013-10-10

申请号：US13713377

申请日：2012-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung-Wan KOH ,  Tae-Kyeong KO

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7208 ,  G11C5/00

Abstract: A non-volatile memory device having respective parallel queues is disclosed. The non-volatile memory device includes a plurality of concurrently addressable units. The non-volatile memory device has respective queues for the concurrently addressable units, and transfers a second command to respective queues for the remaining concurrently addressable units while a first command is executed in a part of the concurrently addressable units, and executes a second command in the remaining concurrently addressable units. Accordingly, non-volatile memory device may concurrently access the concurrently addressable units in parallel, and may have high speed.

Abstract translation: 公开了具有各自的并行队列的非易失性存储器件。 非易失性存储器件包括多个可同时寻址的单元。 非易失性存储器件具有用于同时可寻址单元的各自的队列，并且在同时可寻址单元的一部分中执行第一命令时，将第二命令传送到剩余的可寻址单元的各个队列，并且执行第二命令 剩余的可寻址单元。 因此，非易失性存储装置可以并行地同时访问同时可寻址单元，并且可以具有高速度。

公开(公告)号：US20190310905A1

公开(公告)日：2019-10-10

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong KO ,  Dae-Jeong KIM ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Yongjun YU ,  lnsu CHOI ,  Hui-Chung BYUN ,  JongYoung LEE

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US20190303282A1

公开(公告)日：2019-10-03

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong KIM ,  Jiseok KANG ,  Tae-Kyeong KO ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Wonjae SHIN ,  Yongjun YU ,  Insu CHOI

IPC: G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G11C11/56

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.