公开(公告)号：US20190310905A1

公开(公告)日：2019-10-10

申请号：US16164103

申请日：2018-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonjae Shin ,  Tae-Kyeong KO ,  Dae-Jeong KIM ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Yongjun YU ,  lnsu CHOI ,  Hui-Chung BYUN ,  JongYoung LEE

IPC: G06F11/07

Abstract: A memory system includes a processor that includes cores and a memory controller, and a first semiconductor memory module that communicates with the memory controller. The cores receive a call to perform a first exception handling in response to detection of a first error when the memory controller reads first data from the first semiconductor memory module. A first monarchy core of the cores performs the first exception handling and the remaining cores of the cores return to remaining operations previously performed.

公开(公告)号：US20190303282A1

公开(公告)日：2019-10-03

申请号：US16162821

申请日：2018-10-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dae-Jeong KIM ,  Jiseok KANG ,  Tae-Kyeong KO ,  Sung-Joon KIM ,  Wooseop KIM ,  Chanik PARK ,  Wonjae SHIN ,  Yongjun YU ,  Insu CHOI

IPC: G06F12/02 ,  G06F13/16 ,  G06F3/06 ,  G11C11/56

Abstract: A memory system includes a nonvolatile memory module and a first controller configured to control the nonvolatile memory module. The nonvolatile memory module includes a volatile memory device, a nonvolatile memory device, and a second controller configured to control the volatile memory device and the nonvolatile memory device. The first controller may be configured to transmit a read request to the second controller. When, during a read operation according to the read request, normal data is not received from the nonvolatile memory device, the first controller may perform one or more retransmits of the read request to the second controller without a limitation on a number of times that the first controller performs the one or more retransmits of the read request.