公开(公告)号：US20150235947A1

公开(公告)日：2015-08-20

申请号：US14705416

申请日：2015-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byung-Hyun LEE ,  Hoon LEE

IPC: H01L23/525 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L23/5252 ,  G11C5/04 ,  G11C29/883 ,  H01L22/22 ,  H01L23/481 ,  H01L23/5256 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/06181 ,  H01L2224/13009 ,  H01L2224/16145 ,  H01L2224/32146 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01005 ,  H01L2924/01047 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1441 ,  H01L2924/1443 ,  H01L2924/14511 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2924/00

Abstract: A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Abstract translation: 提供了多芯片封装。 多芯片封装包括多个芯片，其包括至少一个坏芯片和至少一个堆叠好的芯片以及穿过芯片的多个穿通电极。 包含在所述至少一个坏芯片中的逻辑电路与所述多个穿透电极中的每一个绝缘。

公开(公告)号：US20170117887A1

公开(公告)日：2017-04-27

申请号：US15206622

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon LEE ,  Joung-wook MOON ,  Seong-hwan JEON

IPC: H03K5/156 ,  H03L7/089

CPC classification number: H03K5/1565 ,  H03L7/0891

Abstract: A duty cycle corrector (DCC) includes a duty corrector circuit configured to adjust a duty of an input signal to output a duty-adjusted signal; a duty detector circuit configured to generate a correction code associated with the adjustment of the duty, based on a charge pump operation and a counting operation; and a timing controller configured to generate a first control signal associated with the charge pump operation and a second control signal associated with the counting operation in synchronization with a first clock.

公开(公告)号：US20150117122A1

公开(公告)日：2015-04-30

申请号：US14466509

申请日：2014-08-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon LEE ,  Jin-Hee PARK

IPC: H03K19/00 ,  G11C7/12

CPC classification number: H03K19/0005 ,  G11C7/1048 ,  G11C7/1057 ,  G11C7/12 ,  G11C2207/2254

Abstract: Provided is a semiconductor memory device calibrating a termination resistance, the semiconductor memory device comprising self-adjustment logic configured to determine whether a value of an upper bit string of a calibration code generated in response to a calibration start signal is equal to or greater than an upper critical value of the calibration code, or is equal to or less than a lower critical value of the calibration code, and to generate an adjustment signal for adjusting a value of a termination resistance of a data output driver based on the determination result; and resistance calibration logic configured to provide the upper bit string to the self-adjustment logic, and to generate an updated calibration code by performing a calibration calculation based on the calibration code and a comparison signal generated according to a result of comparing a reference voltage and a voltage of a comparison target node.

Abstract translation: 提供了校准端接电阻的半导体存储器件，所述半导体存储器件包括自调整逻辑，其被配置为确定响应于校准开始信号产生的校准代码的高位位串的值是否等于或大于 校准代码的上临界值或者等于或小于校准代码的较低临界值，并且基于确定结果生成用于调整数据输出驱动器的终端电阻的值的调整信号; 以及电阻校准逻辑，被配置为将所述高位串提供给所述自调节逻辑，并且通过基于所述校准代码执行校准计算以及根据比较参考电压和 比较目标节点的电压。