公开(公告)号：US20210265251A1

公开(公告)日：2021-08-26

申请号：US17031141

申请日：2020-09-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungdon MUN ,  Myungsam KANG ,  Youngchan KO ,  Yieok KWON ,  Jeongseok KIM ,  Gongje LEE ,  Bongju CHO

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor package includes a core member having a first surface and a second surface opposing each other, and an external side surface between the first and second surfaces, the core member having a through-hole connecting the first and second surfaces, having a protruding portion that protrudes from the external side surface, and having a surface roughness (Ra) of 0.5 μm or more, a redistribution substrate on the first surface of the core member, and including a redistribution layer; a semiconductor chip in the through-hole on the redistribution substrate, and having a contact pad electrically connected to the redistribution layer, and an encapsulant on the redistribution substrate, and covering the semiconductor chip and the core member, the protruding portion of the core member having a surface exposed to a side surface of the encapsulant.

公开(公告)号：US20240162135A1

公开(公告)日：2024-05-16

申请号：US18215292

申请日：2023-06-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jingu KIM ,  Yieok KWON ,  Wooyoung KIM ,  Gongje LEE ,  Sangkyu LEE ,  Bongju CHO

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/56 ,  H01L23/3128 ,  H01L23/49822 ,  H01L24/16 ,  H01L25/0657 ,  H01L25/50 ,  H01L23/291 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/16227 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06517 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2924/0665

Abstract: A semiconductor package includes a lower redistribution wiring layer; and a first semiconductor device on the lower redistribution wiring layer, the first semiconductor device being connected to the lower redistribution wiring layer via conductive bumps, wherein the lower redistribution wiring layer includes: a first redistribution wire in a first lower insulating layer; an insulating structure layer having an opening that exposes a portion of the first redistribution wire, the insulating structure layer including a first photosensitive insulating layer, a light blocking layer on the first photosensitive insulating layer, and a second photosensitive insulating layer on the light blocking layer; a second redistribution wire in the opening of the insulating structure layer, the second redistribution wire including a redistribution via contacting the first redistribution wire, and a redistribution line stacked on the redistribution via; and bonding pads bonded to the conductive bumps and electrically connected to the second redistribution wire.

公开(公告)号：US20250014957A1

公开(公告)日：2025-01-09

申请号：US18762040

申请日：2024-07-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jingu KIM ,  Gongje LEE ,  Yongjun LEE

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/14 ,  H01L23/26 ,  H01L23/29 ,  H01L23/49 ,  H01L23/498 ,  H01L25/00 ,  H01L25/10

Abstract: A semiconductor package includes: a first redistribution structure including a first redistribution pattern and a first redistribution insulating layer at least partially surrounding the first redistribution pattern; a first semiconductor chip disposed on the first redistribution structure; a first molding member at least partially surrounding the first semiconductor chip and the first redistribution structure; a conductive pillar passing through the first molding member; a second redistribution structure disposed on the first molding member and including a second redistribution pattern and a second redistribution insulating layer at least partially surrounding the second redistribution pattern; a second semiconductor chip disposed on the second redistribution structure; and a second molding member at least partially surrounding the second semiconductor chip and the second redistribution structure.