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    HARD MACRO HAVING BLOCKAGE SITES, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO
    1.
    发明申请
    HARD MACRO HAVING BLOCKAGE SITES, INTEGRATED CIRCUIT INCLUDING SAME AND METHOD OF ROUTING THROUGH A HARD MACRO 审中-公开
    具有闭塞位置的硬件，包括其的集成电路和通过硬盘驱动器路由的方法

    公开(公告)号：US20140131885A1

    公开(公告)日：2014-05-15

    申请号：US13753193

    申请日：2013-01-29

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du ,  Robert P. Gilmore

    IPC: H01L23/498 ,  H01L21/768

    CPC classification number: H01L23/49827 ,  G06F17/5068 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

    Abstract translation: 硬宏包括限定硬宏区域并具有顶部和底部以及从顶部到底部的宏宏厚度的周边，硬宏包括从顶部到底部延伸穿过硬宏厚度的多个通孔。 还有一种具有顶层，底层和至少一个中间层的集成电路，顶层包括顶层导电迹线，中间层包括硬宏，底层包括底层导电迹线，其中顶部 层导电迹线通过延伸穿过硬宏的通孔连接到底层导电迹线。

    3D floorplanning using 2D and 3D blocks
    3.
    发明授权
    3D floorplanning using 2D and 3D blocks 有权
    使用2D和3D块的3D布局规划

    公开(公告)号：US09064077B2

    公开(公告)日：2015-06-23

    申请号：US13792384

    申请日：2013-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F2217/66

    Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

    Abstract translation: 所公开的实施例涉及用于使用提供对现有3D设计方法的显着改进的2D和3D块的混合来布局规划集成电路设计的系统和方法。 所公开的实施例提供了更好的平面图解决方案，其进一步最小化电线长度并提高设计的整体功率/性能包络。 所公开的方法可以用于构建新的3D IP块，以用于使用单片3D集成技术构建的设计中。

    3D FLOORPLANNING USING 2D AND 3D BLOCKS
    4.
    发明申请
    3D FLOORPLANNING USING 2D AND 3D BLOCKS 有权
    使用2D和3D块的3D FLOORPLANNING

    公开(公告)号：US20140149958A1

    公开(公告)日：2014-05-29

    申请号：US13792384

    申请日：2013-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Yang Du

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F2217/66

    Abstract: The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.

    Abstract translation: 所公开的实施例涉及用于使用提供对现有3D设计方法的显着改进的2D和3D块的混合来布局规划集成电路设计的系统和方法。 所公开的实施例提供了更好的平面图解决方案，其进一步最小化电线长度并提高设计的整体功率/性能包络。 所公开的方法可以用于构建新的3D IP块，以用于使用单片3D集成技术构建的设计中。

    Clock distribution network for 3D integrated circuit
    5.
    发明授权
    Clock distribution network for 3D integrated circuit 有权
    时钟分配网络用于3D集成电路

    公开(公告)号：US09098666B2

    公开(公告)日：2015-08-04

    申请号：US13792486

    申请日：2013-03-11

    Applicant: QUALCOMM Incorporated

    Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

    IPC: G06F17/50 ,  H01L23/522 ,  G11C5/14 ,  G06F1/32

    CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

    Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

    Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。

    CLOCK DISTRIBUTION NETWORK FOR 3D INTEGRATED CIRCUIT
    6.
    发明申请
    CLOCK DISTRIBUTION NETWORK FOR 3D INTEGRATED CIRCUIT 有权
    三维集成电路的时钟分配网络

    公开(公告)号：US20140145347A1

    公开(公告)日：2014-05-29

    申请号：US13792486

    申请日：2013-03-11

    Applicant: QUALCOMM INCORPORATED

    Inventor： Kambiz Samadi ,  Shreepad A. Panth ,  Jing Xie ,  Yang Du

    IPC: G06F17/50 ,  H01L23/522

    CPC classification number: G06F17/5072 ,  G06F1/32 ,  G06F1/3287 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5068 ,  G06F17/5077 ,  G06F2217/62 ,  G11C5/14 ,  H01L23/5226 ,  H01L2924/0002 ,  H03K19/0008 ,  H01L2924/00

    Abstract: Exemplary embodiments of the invention are directed to systems and method for designing a clock distribution network for an integrated circuit. The embodiments identify critical sources of clock skew, tightly control the timing of the clock and build that timing into the overall clock distribution network and integrated circuit design. The disclosed embodiments separate the clock distribution network (CDN), i.e., clock generation circuitry, wiring, buffering and registers, from the rest of the logic to improve the clock tree design and reduce the area footprint. In one embodiment, the CDN is separated to a separate tier of a 3D integrated circuit, and the CDN is connected to the logic tier(s) via high-density inter-tier vias. The embodiments are particularly advantageous for implementation with monolithic 3D integrated circuits.

    Abstract translation: 本发明的示例性实施例涉及用于设计用于集成电路的时钟分配网络的系统和方法。 这些实施例确定了时钟偏移的关键来源，紧密地控制时钟的定时并将该时序构建到整个时钟分配网络和集成电路设计中。 所公开的实施例将时钟分配网络（CDN），即时钟生成电路，布线，缓冲和寄存器与逻辑的其余部分分开，以改进时钟树设计并减少面积占用。 在一个实施例中，CDN被分离成3D集成电路的单独层，并且CDN通过高密度层间通孔连接到逻辑层。 这些实施例对于使用单片3D集成电路的实现特别有利。

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