Invention Grant
- Patent Title: 3D floorplanning using 2D and 3D blocks
- Patent Title (中): 使用2D和3D块的3D布局规划
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Application No.: US13792384Application Date: 2013-03-11
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Publication No.: US09064077B2Publication Date: 2015-06-23
- Inventor: Kambiz Samadi , Shreepad A. Panth , Yang Du
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agent Nicholas J. Pauley; Peter Michael Kamarchik; Paul Holdaway
- Main IPC: G06F17/50
- IPC: G06F17/50
Abstract:
The disclosed embodiments are directed to systems and method for floorplanning an integrated circuit design using a mix of 2D and 3D blocks that provide a significant improvement over existing 3D design methodologies. The disclosed embodiments provide better floorplan solutions that further minimize wirelength and improve the overall power/performance envelope of the designs. The disclosed methodology may be used to construct new 3D IP blocks to be used in designs that are built using monolithic 3D integration technology.
Public/Granted literature
- US20140149958A1 3D FLOORPLANNING USING 2D AND 3D BLOCKS Public/Granted day:2014-05-29
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