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    PERFORMANCE OVERHEAD OPTIMIZATION IN GPU SCOPING
    1.
    发明申请
    PERFORMANCE OVERHEAD OPTIMIZATION IN GPU SCOPING 有权

    公开(公告)号：US20230009205A1

    公开(公告)日：2023-01-12

    申请号：US17373718

    申请日：2021-07-12

    Applicant: QUALCOMM Incorporated

    Inventor： Tushar GARG ,  Thomas Edwin FRISINGER ,  Nigel POOLE ,  Vishwanath Shashikant NIKAM ,  Vijay Kumar DONTHIREDDY

    IPC: G06T15/00 ,  G06T1/20 ,  G06F11/34

    Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.

    ELIMINATION CACHE
    2.
    发明公开
    ELIMINATION CACHE 审中-公开

    公开(公告)号：US20240289912A1

    公开(公告)日：2024-08-29

    申请号：US18175480

    申请日：2023-02-27

    Applicant: QUALCOMM Incorporated

    Inventor： Nigel POOLE ,  Zilin YING ,  Xuhui MAO ,  Vijay Kumar DONTHIREDDY ,  Srihari Babu ALLA

    IPC: G06T1/20 ,  G06T1/60

    CPC classification number: G06T1/20 ,  G06T1/60

    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for an elimination cache. A graphics processor may obtain an indication of at least one state update from at least one CP associated with a graphics processor, where the at least one state update corresponds to one or more states in a set of states associated with the graphics processor. The graphics processor may determine whether the one or more states are stored in a cache associated with the graphics processor. The graphics processor may discard the at least one state update based on a determination that the one or more states are stored in the cache or update the cache based on a determination that the one or more states are not stored in the cache.

    METHODS AND APPARATUS FOR GPU CONTEXT REGISTER MANAGEMENT
    4.
    发明申请
    METHODS AND APPARATUS FOR GPU CONTEXT REGISTER MANAGEMENT 审中-公开

    公开(公告)号：US20200279347A1

    公开(公告)日：2020-09-03

    申请号：US16290761

    申请日：2019-03-01

    Applicant: QUALCOMM Incorporated

    Inventor： Nigel POOLE ,  Xuefeng TANG ,  Jian LIANG

    IPC: G06T1/20 ,  G06T1/60

    Abstract: The present disclosure relates to methods and apparatus of operation of a processing unit. The apparatus can update a first context register of one or more context registers based on a first programming state. In some aspects, the one or more context registers can be associated with at least one processing unit cluster in a graphics processing pipeline of the processing unit. The apparatus can execute a first draw call function corresponding to the first programming state. The apparatus can determine whether at least one additional first draw call function corresponds to the first programming state. In some aspects, the at least one additional first draw call function can follow the first draw call function in the graphics processing pipeline. Also, the apparatus can execute the at least one additional first draw call function when the at least one additional first draw call function corresponds to the first programming state.

    SIGNED COMMAND STREAM AND COMMAND EXECUTION
    5.
    发明申请
    SIGNED COMMAND STREAM AND COMMAND EXECUTION 有权

    公开(公告)号：US20220114284A1

    公开(公告)日：2022-04-14

    申请号：US17070734

    申请日：2020-10-14

    Applicant: QUALCOMM Incorporated

    Inventor： Avinash SEETHARAMAIAH ,  Murat BALCI ,  Jonnala Gadda NAGENDRA KUMAR ,  Nigel POOLE ,  Abhiraj DESHPANDE

    IPC: G06F21/64 ,  G06F21/52 ,  G06F21/56 ,  G06F21/71

    Abstract: Systems, methods, and computer-readable media are provided for signing and executing graphics processing unit (GPU) commands. In some examples, a method can include receiving, by a GPU, one or more commands including one or more verification signatures generated using a processor, each verification signature of the one or more verification signatures including a first value generated based on the one or more commands; generating, by the GPU, one or more additional verification signatures associated with the one or more commands, wherein each verification signature of the one or more additional verification signatures includes a second value generated by the GPU based on the one or more commands; and determining, by the GPU, a validity of the one or more commands based on a comparison of the one or more verification signatures and the one or more additional verification signatures.

    DEFERRED COMMAND EXECUTION
    7.
    发明申请
    DEFERRED COMMAND EXECUTION 有权

    公开(公告)号：US20210389950A1

    公开(公告)日：2021-12-16

    申请号：US16900814

    申请日：2020-06-12

    Applicant: QUALCOMM Incorporated

    Inventor： Nigel POOLE ,  Joohi MITTAL

    IPC: G06F9/38 ,  G06F13/28

    Abstract: Deferred command execution by a command processor (CP) may be performed based on a determination that at least one command of a primary buffer is located between a first link of the primary buffer and a second link of the primary buffer. The first link and the second link may be to one or more secondary buffers that includes a set of commands. The CP may initiate, before executing, a fetch of a first set of commands in the set of commands based on the first link, a fetch of the at least one command of the primary buffer, and a fetch of a second set of commands in the set of commands based on the second link. After initiating the fetch of the second set of commands, the CP may execute the first set of commands, the at least one command of the primary buffer, and the second set of commands.

    CONCURRENT BINNING AND RENDERING
    8.
    发明申请
    CONCURRENT BINNING AND RENDERING 审中-公开

    公开(公告)号：US20200020067A1

    公开(公告)日：2020-01-16

    申请号：US16035372

    申请日：2018-07-13

    Applicant: QUALCOMM Incorporated

    Inventor： Jian LIANG ,  Tao WANG ,  Chun YU ,  Andrew Evan GRUBER ,  Donghyun KIM ,  Nigel POOLE ,  Tzun-Wei LEE ,  Shambhoo KHANDELWAL

    IPC: G06T1/20 ,  G06T15/00 ,  G06T1/60

    Abstract: A method, an apparatus, and a computer-readable medium may be configured to perform a binning pass for a first frame. The apparatus may be configured to perform a rendering pass for the first frame in parallel with the binning pass. The apparatus may be configured to enhance efficiency in performing a binning pass and a rendering pass for tile-based rendering, such that the binning pass and rendering pass are performed concurrently. The apparatus may be configured to perform the binning pass using a first hardware pipeline, and may be configured to perform the rendering pass using a second hardware pipeline.

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