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公开(公告)号:US20210120248A1
公开(公告)日:2021-04-22
申请号:US17104353
申请日:2020-11-25
Applicant: QUALCOMM Incorporated
Inventor: In Suk CHONG , Xianglin WANG , Cheng-Teh HSIEH
IPC: H04N19/13 , H03M7/30 , G06N3/02 , H04L29/06 , H04N19/176
Abstract: Techniques and systems are provided for compressing data in a neural network. For example, output data can be obtained from a node of the neural network. Re-arranged output data having a re-arranged scanning pattern can be generated. The re-arranged output data can be generated by re-arranging the output data into the re-arranged scanning pattern. One or more residual values can be determined for the re-arranged output data by applying a prediction mode to the re-arranged output data. The one or more residual values can then be compressed using a coding mode.
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公开(公告)号:US20210288660A1
公开(公告)日:2021-09-16
申请号:US17333282
申请日:2021-05-28
Applicant: QUALCOMM Incorporated
Inventor: Clara Ka Wah SUNG , Meghal VARIA , Serag GADELRAB , Cheng-Teh HSIEH , Jason Edward PODAIMA , Victor SZETO , Richard BOISJOLY , Milivoje ALEKSIC , Tom LONGO , In-Suk CHONG
Abstract: Various embodiments include methods and devices for implementing decompression of compressed high dynamic ratio fields. Various embodiments may include receiving compressed first and second sets of data fields, decompressing the first and second compressed sets of data fields to generate first and second decompressed sets of data fields, receiving a mapping for mapping the first and second decompressed sets of data fields to a set of data units, aggregating the first and second decompressed sets of data fields using the mapping to generate a compression block comprising the set of data units.
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公开(公告)号:US20200274549A1
公开(公告)日:2020-08-27
申请号:US16798186
申请日:2020-02-21
Applicant: QUALCOMM Incorporated
Inventor: Clara Ka Wah SUNG , Meghal VARIA , Serag GADELRAB , Cheng-Teh HSIEH , Jason Edward PODAIMA , Victor SZETO , Richard BOISJOLY , Milivoje ALEKSIC , Tom LONGO , In-Suk CHONG
Abstract: Various embodiments include methods and devices for implementing compression of high dynamic ratio fields. Various embodiments may include receiving a compression block having data units, receiving a mapping for the compression block, wherein the mapping is configured to map bits of each data unit to two or more data fields to generate a first set of data fields and a second set of data fields, compressing the first set of data fields together to generate a compressed first set of data fields, and compressing the second set of data fields together to generate a compressed second set of data fields.
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公开(公告)号:US20250005799A1
公开(公告)日:2025-01-02
申请号:US18346097
申请日:2023-06-30
Applicant: QUALCOMM Incorporated
Inventor: Cheng-Teh HSIEH , Venkata Meher Satchit Anand KOTRA , Hyung Joon KIM , Wei-Jung CHIEN
Abstract: Aspects presented herein relate to methods and devices for data processing including an apparatus, e.g., a CPU. The apparatus may obtain an indication of a set of data subunits corresponding to at least one data unit. The apparatus may also arrange data for the set of data subunits into a first data order for the set of data subunits. Further, the apparatus may perform at least one of an encoding process or a decoding process on the data for each data subunit of the set of data subunits. The apparatus may also rearrange the data for the set of data subunits into the first data order for a first data subunit in the set of data subunits and into a second data order for at least one second data subunit in the set of data subunits, where the first data order is different from the second data order.
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公开(公告)号:US20220254070A1
公开(公告)日:2022-08-11
申请号:US17169342
申请日:2021-02-05
Applicant: QUALCOMM Incorporated
Inventor: Ankitesh Kumar SINGH , Cheng-Teh HSIEH , Marta KARCZEWICZ
Abstract: The present disclosure relates to methods and devices for data or graphics processing including an apparatus, e.g., a GPU. The apparatus may receive at least one bitstream including a plurality of bits, each of the bits corresponding to a position in the at least one bitstream, and each of the bits being associated with color data. The apparatus may also arrange an order of the plurality of bits in the at least one bitstream, such that at least one of the bits corresponds to an updated position in the at least one bitstream. Additionally, the apparatus may convert, upon arranging the order of the bits, the color data associated with each of the plurality of bits in the at least one bitstream. The apparatus may also compress, upon converting the color data associated with each of the bits, the plurality of bits in the at least one bitstream.
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公开(公告)号:US20200186830A1
公开(公告)日:2020-06-11
申请号:US16705027
申请日:2019-12-05
Applicant: QUALCOMM Incorporated
Inventor: Vadim SEREGIN , Cheng-Teh HSIEH , Wei-Jung CHIEN , Marta KARCZEWICZ
IPC: H04N19/573 , H04N19/513 , H04N19/159 , H04N19/46 , H04N19/132 , H04N19/105 , H04N19/186 , H04N19/176
Abstract: Systems and techniques for performing illumination compensation in processing video data include deriving one or more illumination compensation parameters for a block of a picture based on one or more tools which may be used for inter-prediction of the block. Illumination compensation can be selectively applied for the block based on whether bi-directional prediction is to be applied for the inter-prediction of the block. In some cases if it is determined that bi-directional prediction is to be applied for inter-prediction of the block, illumination compensation may be avoided for the block.
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公开(公告)号:US20240205433A1
公开(公告)日:2024-06-20
申请号:US18066087
申请日:2022-12-14
Applicant: QUALCOMM Incorporated
Inventor: Hyung Joon KIM , Wei-Jung CHIEN , Cheng-Teh HSIEH , Marta KARCZEWICZ , Natan JACOBSON , Tao WANG , Clara Ka Wah SUNG , Andrew Edmund TURNER
IPC: H04N19/34 , H04N19/124 , H04N19/60
CPC classification number: H04N19/34 , H04N19/124 , H04N19/60
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for truncation error signaling and adaptive dither for lossy bandwidth compression. A processor may perform a truncation process for data, where the data is associated with display processing, image processing, or the data processing, where the truncation process for the data results in truncated data. The processor may compute a set of truncation error values associated with the truncation process for the truncated data. The processor may generate a set of residual samples for the truncated data. The processor may generate a bitstream based on the set of residual samples for the truncated data and the set of truncation error values associated with the truncation process.
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公开(公告)号:US20200221078A1
公开(公告)日:2020-07-09
申请号:US16725487
申请日:2019-12-23
Applicant: QUALCOMM Incorporated
Inventor: Vadim SEREGIN , Nan HU , Cheng-Teh HSIEH , Marta KARCZEWICZ
IPC: H04N19/105 , H04N19/132 , H04N19/30 , H04N19/186 , H04N19/176
Abstract: Techniques are described herein for processing video data. For instance, a current block of a picture of the video data can be obtained, and it can be determined that the current block includes more than one virtual pipeline data unit (VPDU). Current neighbor samples for the current block, reference neighbor samples for the current block, and additional neighbor samples for the current block can be obtained for illumination compensation. One or more illumination compensation parameters can be determined for the current block using the current neighbor samples, the reference neighbor samples, and the additional neighbor samples. The additional neighbor samples are used for determining the one or more illumination compensation parameters based on the current block covering more than one VPDU. Illumination compensation can be performed for the current block using the one or more illumination compensation parameters.
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公开(公告)号:US20200098138A1
公开(公告)日:2020-03-26
申请号:US16140108
申请日:2018-09-24
Applicant: QUALCOMM Incorporated
Inventor: In Suk CHONG , Xianglin WANG , Cheng-Teh HSIEH
IPC: G06T9/00 , H03M7/24 , G06F7/483 , H04N19/124 , H04N19/182
Abstract: Certain aspects of the present disclosure provide a method of encoding data. The method generally includes receiving data comprising a fractional number comprising an exponential component and a fractional component, the exponential component being represented by an exponential bit sequence, the fractional component being represented by a fractional bit sequence. The method further includes determining if the fractional component is within a threshold of 0 or 1. The method further includes setting the fractional component to 0 when the fractional component is within the threshold of 0 or 1. The method further includes downscaling the fractional bit sequence based on a difference between the exponential component and a second threshold. The method further includes encoding the data. The method further includes transmitting the encoded data.
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公开(公告)号:US20190373264A1
公开(公告)日:2019-12-05
申请号:US15991685
申请日:2018-05-29
Applicant: QUALCOMM Incorporated
Inventor: In Suk CHONG , Xianglin WANG , Cheng-Teh HSIEH
IPC: H04N19/13 , H03M7/30 , H04N19/176 , H04L29/06 , G06N3/02
Abstract: Techniques and systems are provided for compressing data in a neural network. For example, output data can be obtained from a node of the neural network. Re-arranged output data having a re-arranged scanning pattern can be generated. The re-arranged output data can be generated by re-arranging the output data into the re-arranged scanning pattern. One or more residual values can be determined for the re-arranged output data by applying a prediction mode to the re-arranged output data. The one or more residual values can then be compressed using a coding mode.
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