公开(公告)号：US09632781B2

公开(公告)日：2017-04-25

申请号：US13777297

申请日：2013-02-26

Applicant: Qualcomm Incorporated

Inventor： Ajay A. Ingle ,  Marc M. Hoffman ,  Jose Fridman ,  Lucian Codrescu

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/345

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

公开(公告)号：US20140258680A1

公开(公告)日：2014-09-11

申请号：US13785017

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay Anant Ingle ,  Lucian Codrescu ,  Suresh K. Venkumahanti ,  Jose Fridman

IPC: G06F9/38

CPC classification number: G06F9/3881 ,  G06F9/3802

Abstract: Techniques are addressed for parallel dispatch of coprocessor and thread instructions to a coprocessor coupled to a threaded processor. A first packet of threaded processor instructions is accessed from an instruction fetch queue (IFQ) and a second packet of coprocessor instructions is accessed from the IFQ. The IFQ includes a plurality of thread queues that are each configured to store instructions associated with a specific thread of instructions. A dispatch circuit is configured to select the first packet of thread instructions from the IFQ and the second packet of coprocessor instructions from the IFQ and send the first packet to a threaded processor and the second packet to the coprocessor in parallel. A data port is configured to share data between the coprocessor and a register file in the threaded processor. Data port operations are accomplished without affecting operations on any thread executing on the threaded processor.

Abstract translation: 解决了将协处理器和线程指令并行调度到耦合到线程处理器的协处理器的技术。 从指令队列（IFQ）访问第一个线程处理器指令包，并从IFQ访问第二个协处理器指令包。 IFQ包括多个线程队列，每个线程队列被配置为存储与特定指令线程相关联的指令。 调度电路被配置为从IFQ和来自IFQ的协处理器指令的第二分组选择线程指令的第一分组，并且将第一分组并行地发送到线程处理器，并将第二分组发送到协处理器。 数据端口被配置为在协处理器和线程处理器中的寄存器文件之间共享数据。 完成数据端口操作，而不影响在线程处理器上执行的任何线程的操作。

公开(公告)号：US09363749B2

公开(公告)日：2016-06-07

申请号：US13968153

申请日：2013-08-15

Applicant: QUALCOMM Incorporated

Inventor： Deepak Mathew ,  Garret Webster Shih ,  Jose Fridman ,  Robin Lee Brown

IPC: H04B7/00 ,  H04W52/02

CPC classification number: H04W52/02 ,  H04W52/0245 ,  H04W52/028 ,  H04W52/0287 ,  Y02D70/00 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/146

Abstract: A system and method dynamically scale power consumed by the circuitry of an electronic device based on channel state and/or data rate. The electronic device then operates according to the power scaling. The scaling may be in accordance with an effective data rate, a number of multiple input multiple output (MIMO) layers, receiver type, a cell scenario, or a number of carriers. A number of MIMO layers can be predicted based on at least one of channel conditions or a channel quality index (CQI).

Abstract translation: 系统和方法基于信道状态和/或数据速率来动态地缩放由电子设备的电路消耗的功率。 电子设备然后根据功率缩放来操作。 缩放可以根据有效数据速率，多输入多输出（MIMO）层，接收器类型，单元方案或多个载波来实现。 可以基于信道条件或信道质量指数（CQI）中的至少一个来预测多个MIMO层。

公开(公告)号：US20140281421A1

公开(公告)日：2014-09-18

申请号：US13842751

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Marc M. Hoffman ,  Ajay Anant Ingle ,  Jose Fridman

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

Abstract translation: 更新输出数据向量的示例方法包括识别包括元素数据值的数据值向量。 该方法还包括识别包括一组元素的地址值向量。 该方法还包括将条件运算符应用于地址值向量中的该组元素的每个元素。 该方法还包括数据值向量中的每个元素数据值，基于应用条件运算符来确定是否更新输出数据向量。

公开(公告)号：US20140244967A1

公开(公告)日：2014-08-28

申请号：US13777297

申请日：2013-02-26

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay A. Ingle ,  Marc M. Hoffman ,  Jose Fridman ,  Lucian Codrescu

IPC: G06F9/30

CPC classification number: G06F9/30105 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30163 ,  G06F9/345 ,  G06F9/3885

Abstract: Techniques are provided for executing a vector alignment instruction. A scalar register file in a first processor is configured to share one or more register values with a second processor, the one or more register values accessed from the scalar register file according to an Rt address specified, in a vector alignment instruction, wherein a start location is determined from one of the shared register values. An alignment circuit in the second processor is configured to align data identified between the start location within a beginning Vu register of a vector register file (VRF) and an end location of a last Vu register of the VRF according to the vector alignment instruction. A store circuit is configured to select the aligned data from the alignment circuit and store the aligned data in the vector register file according to an alignment store address specified by the vector alignment instruction.

Abstract translation: 提供了用于执行向量对齐指令的技术。 第一处理器中的标量寄存器文件被配置为与向第二处理器共享一个或多个寄存器值，所述寄存器值是根据在矢量对准指令中指定的Rt地址从标量寄存器文件访问的一个或多个寄存器值，其中开始 从共享寄存器值之一确定位置。 第二处理器中的对准电路被配置为根据向量对准指令将矢量寄存器文件（VRF）的起始Vu寄存器内的起始位置与VRF的最后一个Vu寄存器的结束位置之间标识的数据进行对准。 存储电路被配置为从对准电路中选择对准的数据，并根据由向量对准指令指定的对准存储地址将对准的数据存储在向量寄存器文件中。

公开(公告)号：US09639356B2

公开(公告)日：2017-05-02

申请号：US13842751

申请日：2013-03-15

Applicant: QUALCOMM Incorporated

Inventor： Marc M. Hoffman ,  Ajay Anant Ingle ,  Jose Fridman

IPC: G06F9/30

CPC classification number: G06F9/30032 ,  G06F9/30036 ,  G06F9/30072

Abstract: An example method of updating an output data vector includes identifying a data value vector including element data values. The method also includes identifying an address value vector including a set of elements. The method further includes applying a conditional operator to each element of the set of elements in the address value vector. The method also includes for each element data value in the data value vector, determining whether to update an output data vector based on applying the conditional operator.

公开(公告)号：US20140281368A1

公开(公告)日：2014-09-18

申请号：US13829503

申请日：2013-03-14

Applicant: QUALCOMM INCORPORATED

Inventor： Ajay Anant Ingle ,  Lucian Codrescu ,  David J. Hoyle ,  Jose Fridman ,  Marc M. Hoffman ,  Deepak Mathew

IPC: G06F9/30

CPC classification number: G06F9/3853

Abstract: An example method for executing multiple instructions in one or more slots includes receiving a packet including multiple instructions and executing the multiple instructions in one or more slots in a time shared manner. Each slot is associated with an execution data path or a memory data path. An example method for executing at least one instruction in a plurality of phases includes receiving a packet including an instruction, splitting the instruction into a plurality of phases, and executing the instruction in the plurality of phases.

Abstract translation: 用于在一个或多个时隙中执行多个指令的示例性方法包括接收包括多个指令的分组，并以时间共享的方式在一个或多个时隙中执行多个指令。 每个时隙与执行数据路径或存储器数据路径相关联。 用于执行多个阶段中的至少一个指令的示例性方法包括：接收包括指令的分组，将指令分解成多个阶段，以及执行多个阶段中的指令。