公开(公告)号：US20140225223A1

公开(公告)日：2014-08-14

申请号：US13764811

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a metal-insulator-metal (MIM) capacitor reduces the number of masks and processing steps compared to conventional techniques. A conductive redistribution layer (RDL) is patterned on a semiconductor chip. A MIM dielectric layer is deposited over the RDL. A first conductive layer of a MIM capacitor is deposited over the MIM dielectric layer. The MIM dielectric layer is patterned using a MIM conductive layer mask. The conductive redistribution layer includes two RDL nodes that extend under the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与传统技术相比，制造金属 - 绝缘体 - 金属（MIM）电容器的方法减少了掩模和处理步骤的数量。 在半导体芯片上构图导电再分布层（RDL）。 MIM电介质层沉积在RDL上。 在MIM电介质层上沉积MIM电容器的第一导电层。 使用MIM导电层掩模对MIM电介质层进行构图。 导电再分配层包括在MIM电容器的第一导电层下延伸的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US20140197520A1

公开(公告)日：2014-07-17

申请号：US13743434

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  Bin Yang ,  Giridhar Nallapati ,  PR Chidambaram

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L28/24

Abstract: In a particular embodiment, a method includes removing a first portion of an optical planarization layer using a lithographic mask to expose a region of the optical planarization layer. A resistive layer is formed at least partially within the region. The method further includes removing at least a second portion of the optical planarization layer and at least a third portion of the resistive layer to form a resistor.

Abstract translation: 在特定实施例中，一种方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露光学平坦化层的区域。 至少部分地在该区域内形成电阻层。 该方法还包括去除光学平坦化层的至少第二部分和电阻层的至少第三部分以形成电阻器。

公开(公告)号：US09252104B2

公开(公告)日：2016-02-02

申请号：US14512191

申请日：2014-10-10

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Bin Yang ,  Pr Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L29/00 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的下互连层。 CBC结构还包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上部互连层和第二上部互连层之间的金属绝缘体金属（MIM）电容器层。 此外，CBC结构还包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。

公开(公告)号：US20140001568A1

公开(公告)日：2014-01-02

申请号：US13684107

申请日：2012-11-21

Applicant: QUALCOMM INCORPORATED

Inventor： Zhongze Wang ,  John J. Zhu ,  Xia Li

IPC: H01L27/112 ,  H01L21/8239

CPC classification number: H01L27/11206 ,  G11C17/16 ,  G11C17/165 ,  H01L21/8239 ,  H01L23/5228 ,  H01L23/5252 ,  H01L27/1052 ,  H01L27/11286 ,  H01L28/24 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One feature pertains to an integrated circuit, comprising an access transistor and an antifuse. The access transistor includes at least one source/drain region, and the antifuse has a conductor-insulator-conductor structure. The antifuse includes a first conductor that acts as a first electrode, and also includes an antifuse dielectric, and a second conductor. A first surface of the first electrode is coupled to a first surface of the antifuse dielectric, a second surface of the antifuse dielectric is coupled to a first surface of the second conductor. The second conductor is electrically coupled to the access transistor's source/drain region. The antifuse is adapted to transition from an open circuit state to a closed circuit state if a programming voltage Vpp greater than or equal to an antifuse dielectric breakdown voltage is applied between the first electrode and the second conductor.

Abstract translation: 一个特征涉及一种集成电路，包括存取晶体管和反熔丝。 存取晶体管包括至少一个源极/漏极区域，反熔丝具有导体 - 绝缘体 - 导体结构。 反熔丝包括用作第一电极的第一导体，并且还包括反熔丝电介质和第二导体。 第一电极的第一表面耦合到反熔丝电介质的第一表面，反熔丝电介质的第二表面耦合到第二导体的第一表面。 第二导体电耦合到存取晶体管的源/漏区。 如果在第一电极和第二导体之间施加大于或等于抗熔丝电介质击穿电压的编程电压Vpp，则反熔丝适于从开路状态转换到闭合电路状态。

公开(公告)号：US09287347B2

公开(公告)日：2016-03-15

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  P R Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L29/49 ,  H01L49/02 ,  H01L23/64 ,  H01L23/522

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US08980708B2

公开(公告)日：2015-03-17

申请号：US13770127

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： John J. Zhu ,  Bin Yang ,  P R Chidambaram ,  Lixin Ge ,  Jihong Choi

IPC: H01L21/8244 ,  H01L23/538 ,  H01L27/08 ,  H01L49/02 ,  H01L23/522

CPC classification number: H01L23/538 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes at least one lower interconnect layer of the interconnect stack. The CBC structure may also include a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes at least one metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure may also include a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having at least a portion of the first upper interconnect layer, and a second capacitor plate having at least a portion of the MIM capacitor layer(s).

Abstract translation: 互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的至少一个下互连层。 CBC结构还可以包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上互连层和第二上互连层之间的至少一个金属绝缘体金属（MIM）电容器层。 此外，CBC结构还可以包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的至少一部分的第一电容器板和具有至少一部分MIM电容器层的第二电容器板。

公开(公告)号：US20140312500A1

公开(公告)日：2014-10-23

申请号：US13864344

申请日：2013-04-17

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  Zhongze Wang ,  Yang Da

IPC: H01L21/283 ,  H01L21/768 ,  H01L23/50

CPC classification number: H01L21/76894 ,  G03F7/7045 ,  G03F7/70466 ,  H01L21/28123 ,  H01L21/283 ,  H01L21/31 ,  H01L21/469 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/50 ,  H01L24/27 ,  H01L24/31 ,  H01L2924/0002 ,  H01L2924/12042 ,  H01L2924/00

Abstract: Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.

Abstract translation: 特征是在半导体芯片上制造的。 这些特征小于用于制造芯片的光刻的阈值。 一种方法包括图案化特征（例如局部互连）的第一部分和要被分离预定距离的特征的第二部分，例如线尖到尖端空间或线空间。 该方法还包括用切割掩模图案化第一部分以形成第一子部分（例如，接触）和第二子部分。 第一子部分的尺寸小于第二预定距离的尺寸，其可以是具有指定宽度分辨率的光刻工艺的线长分辨率。 半导体器件的特征包括第一部分和具有小于第一部分的光刻分辨率的尺寸的第二部分。

公开(公告)号：US20140225224A1

公开(公告)日：2014-08-14

申请号：US13765015

申请日：2013-02-12

Applicant: QUALCOMM INCORPORATED

Inventor： John J. Zhu ,  PR Chidambaram ,  Giridhar Nallapati ,  Choh fei Yeap

IPC: H01L49/02

CPC classification number: H01L28/40 ,  H01L23/5223 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal-insulator-metal (MIM) capacitor reduces a number of masks and processing steps compared to conventional techniques. A first conductive layer of a MIM capacitor is deposited on a semiconductor chip and patterned using a MIM conductive layer mask. A conductive redistribution layer (RDL) is patterned over the MIM dielectric layer. The conductive redistribution layer includes two RDL nodes that overlap the first conductive layer of the MIM capacitor. A conductive via or bump extends through the MIM dielectric layer and couples one of the RDL nodes to the first conductive layer of the MIM capacitor.

Abstract translation: 与常规技术相比，金属 - 绝缘体 - 金属（MIM）电容器减少了许多掩模和处理步骤。 MIM电容器的第一导电层沉积在半导体芯片上并使用MIM导电层掩模进行图案化。 导电再分配层（RDL）在MIM介电层上图案化。 导电再分配层包括与MIM电容器的第一导电层重叠的两个RDL节点。 导电通孔或凸块延伸穿过MIM介电层，并将RDL节点之一耦合到MIM电容器的第一导电层。

公开(公告)号：US20140203404A1

公开(公告)日：2014-07-24

申请号：US13745962

申请日：2013-01-21

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02

CPC classification number: H01L28/87 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Spiral metal-on-metal (MoM or SMoM) capacitors and related systems and methods of forming MoM capacitors are disclosed. In one embodiment, a MoM capacitor disposed in a semiconductor die is disclosed. The MoM capacitor comprises a first electrode coupled to a first trace. The first trace is coiled in a first inwardly spiraling pattern and comprised of first parallel trace segments. The MoM capacitor also comprises a second electrode coupled to a second trace. The second trace is coiled in the first inwardly spiraling pattern and comprised of second parallel trace segments interdisposed between the first parallel trace segments. Reduced variations in the capacitance allow circuit designers to build circuits with tighter tolerances and generally improve circuit reliability.

Abstract translation: 公开了形成MoM电容器的螺旋金属金属（MoM或SMoM）电容器及相关系统和方法。 在一个实施例中，公开了一种设置在半导体管芯中的MoM电容器。 MoM电容器包括耦合到第一迹线的第一电极。 第一迹线卷绕在第一向内螺旋形的图案中并由第一平行迹线段组成。 MoM电容器还包括耦合到第二迹线的第二电极。 第二迹线卷绕在第一向内螺旋形图案中，并且包括间隔在第一平行迹线段之间的第二平行迹线段。 降低电容的变化允许电路设计者构建更严格公差的电路，并且通常提高电路的可靠性。

公开(公告)号：US20140197519A1

公开(公告)日：2014-07-17

申请号：US13743388

申请日：2013-01-17

Applicant: QUALCOMM INCORPORATED

Inventor： Jihong Choi ,  John J. Zhu ,  PR Chidambaram ,  Bin Yang ,  Lixin Ge

IPC: H01L49/02 ,  G06F17/50

CPC classification number: H01L28/92

Abstract: In a particular embodiment, a method of forming a metal-insulator-metal (MIM) capacitor includes removing, using a lithographic mask, a first portion of an optical planarization layer to expose a region in which the MIM capacitor is to be formed. A second portion of an insulating layer is formed on a first conductive layer that is formed on a plurality of trench surfaces within the region. The method further includes removing at least a third portion of the insulating layer according to a lift-off technique.

Abstract translation: 在特定实施例中，形成金属 - 绝缘体 - 金属（MIM）电容器的方法包括使用光刻掩模去除光学平坦化层的第一部分以暴露其中将形成MIM电容器的区域。 绝缘层的第二部分形成在形成在该区域内的多个沟槽表面上的第一导电层上。 该方法还包括根据剥离技术去除绝缘层的至少第三部分。