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公开(公告)号：US20220414814A1
公开(公告)日：2022-12-29
申请号：US17356434
申请日：2021-06-23
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Chihong ZHANG , Jian JIANG , Gang ZHONG , Baoguang YANG , Yang XIA , Chun YU , Eric DEMERS
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may generate a table including a plurality of entries to store data associated with at least one of a constant value or an immediate value. The apparatus may also process, upon generating the table, first data including at least one of a constant value or an immediate value. Further, the apparatus may store, in the generated table, at least one of the constant value or the immediate value of the first data. The apparatus may also transmit, upon storing at least one of the constant value or the immediate value in the table, the table including the stored at least one of the constant value or the immediate value of the first data.
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公开(公告)号：US20210209717A1
公开(公告)日：2021-07-08
申请号：US16734252
申请日：2020-01-03
Applicant: QUALCOMM INCORPORATED
Inventor： Yun DU , Chun YU , Andrew Evan GRUBER , Zilin YING , Baoguang YANG
Abstract: Methods, systems, and devices for image processing are described. A device may determine, based on a test operation, to terminate a first wave associated with a first slot of a set of slots. The device may update a terminated wave bit associated with the first slot based on the determination to terminate the first wave. In some aspects, the device may update a number of invocations field associated with the first wave based on the determination to terminate the first wave. The device may release the first slot based on updating the terminated wave bit and the number of invocations field. In some examples, the device may output the number of invocations field to a rendering backend of the device based on the terminated wave bit.
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公开(公告)号：US20240212257A1
公开(公告)日：2024-06-27
申请号：US18145804
申请日：2022-12-22
Applicant: QUALCOMM Incorporated
Inventor： Liang LI , Andrew Evan GRUBER , Baoguang YANG
CPC classification number: G06T15/04 , G06T1/20 , G06T15/005
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for workload packing in a graphics texture pipeline. A graphics processor may combine a set of samples into one or more hardware transactions, where the set of samples is associated with at least one of a first type of texture filtering or a first type of shader requested texture format component and the one or more hardware transactions are associated with at least one of a second type of texture filtering or a second type of shader requested texture format component. The graphics processor may process, in a texture pipeline at the graphics processor, the one or more hardware transactions including the set of samples. The graphics processor may output an indication of the processed one or more hardware transactions including the set of samples.
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Patent Agency Ranking
公开(公告)号：US20230377240A1
公开(公告)日：2023-11-23
申请号：US17664033
申请日：2022-05-18
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Eric DEMERS , Andrew Evan GRUBER , Chun YU , Chihong ZHANG , Baoguang YANG , Yuehai DU , Gang ZHONG , Avinash SEETHARAMAIAH , Jonnala Gadda NAGENDRA KUMAR
CPC classification number: G06T15/005 , G06T1/60
Abstract: Aspects presented herein relate to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a set of draw call instructions corresponding to a graphics workload, where the set of draw call instructions is associated with at least one run-time parameter. The apparatus may also obtain a first shader program associated with storing data in a system memory and at least one second shader program associated with storing data in a constant memory. Further, the apparatus may execute the first shader program or the at least one second shader program based on whether the at least one run-time parameter is less than or equal to a size of the constant memory. The apparatus may also update or maintain a configuration of a shader processor or a streaming processor based on executing the first shader program or the at least one second shader program.
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公开(公告)号：US20220357983A1
公开(公告)日：2022-11-10
申请号：US17315205
申请日：2021-05-07
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Zilin YING , Gang ZHONG , Baoguang YANG , Yang YU , Yang XIA , Ravindra KUMAR , Chun YU , Eric DEMERS
IPC: G06F9/48 , G06F12/0875 , G06T1/20
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may receive a plurality of workloads based on a workload order, each of the plurality of workloads being received in the workload order including at least a first workload and a second workload. The apparatus may also allocate one or more workloads of the plurality of workloads to one or more wave slots. Additionally, the apparatus may execute the one or more allocated workloads at the one or more wave slots, such that at least the first workload is executed at the first wave slot and the second workload is executed at the second wave slot. The apparatus may also allocate at least one other workload of the plurality of workloads to at least one previously-allocated wave slot of the one or more wave slots.
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公开(公告)号：US20240046543A1
公开(公告)日：2024-02-08
申请号：US17817815
申请日：2022-08-05
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Eric DEMERS , Andrew Evan GRUBER , Chun YU , Baoguang YANG , Chihong ZHANG , Yuehai DU , Avinash SEETHARAMAIAH , Jonnala Gadda NAGENDRA KUMAR , Gang ZHONG , Zilin YING , Fei WEI
CPC classification number: G06T15/005 , G06T15/80
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for runtime optimization of the shader execution flow. A graphics processor may obtain instruction execution data associated with a graphics workload, the instruction execution data including graphics data for a set of shader operations. The graphics processor may configure, at a first iteration, at least one predication value based on the instruction execution data including the graphics data for the set of shader operations. The graphics processor may adjust, at a second iteration, an execution flow of the graphics workload based on the configured at least one predication value, the execution flow of the graphics workload including the set of shader operations. The graphics processor may execute or refrain from executing, at the second iteration, each of the set of shader operations based on the adjusted execution flow of the graphics workload.
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公开(公告)号：US20230267567A1
公开(公告)日：2023-08-24
申请号：US17652478
申请日：2022-02-24
Applicant: QUALCOMM Incorporated
Inventor： Yun DU , Andrew Evan GRUBER , Zilin YING , Chunling HU , Baoguang YANG , Yang XIA , Gang ZHONG , Chun YU , Eric DEMERS
Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for dynamic wave pairing. A graphics processor may allocate one or more GPU workloads to one or more wave slots of a plurality of wave slots. The graphics processor may select a first execution slot of a plurality of execution slots for executing the one or more GPU workloads. The selection may be based on one of a plurality of granularities. The graphics processor may execute, at the selected first execution slot, the one or more GPU workloads at the one of the plurality of granularities.
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公开(公告)号：US20230017522A1
公开(公告)日：2023-01-19
申请号：US17373704
申请日：2021-07-12
Applicant: QUALCOMM Incorporated
Inventor： Sreyas KURUMANGHAT , Kalyan Kumar BHIRAVABHATLA , Andrew Evan GRUBER , Tao WANG , Baoguang YANG , Pavan Kumar AKKARAJU
Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may configure a portion of a GPU to include at least one depth processing block, the at least one depth processing block being associated with at least one depth buffer. The apparatus may also identify one or more depth passes of each of a plurality of graphics workloads, the plurality of graphics workloads being associated with a plurality of frames. Further, the apparatus may process each of the one or more depth passes in the portion of the GPU including the at least one depth processing block, each of the one or more depth passes being processed by the at least one depth processing block, the one or more depth passes being associated with the at least one depth buffer.
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