公开(公告)号：US20190391762A1

公开(公告)日：2019-12-26

申请号：US16441606

申请日：2019-06-14

Applicant: Panasonic Intellectual Property Management Co. Ltd.

Inventor： Shigekazu KOGITA ,  Toshiyuki HONDA ,  Hirokazu SO ,  Masato SUTO

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

Abstract: A memory controller includes an address converter configured to convert an address designated by a host device for writing and reading into a physical address of a non-volatile memory, and an invalid-area manager configured to manage an invalid area of the non-volatile memory, the address converter making no reference to the invalid area, and, upon receipt of an invalid-data read command from the host device, data in the invalid area, managed by the invalid-area manager, of the non-volatile memory is output to the host device.

公开(公告)号：US20160283163A1

公开(公告)日：2016-09-29

申请号：US15079901

申请日：2016-03-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hirokazu SO ,  Toshiyuki HONDA ,  Shigekazu KOGITA

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/064 ,  G06F12/0246

Abstract: A memory controller includes: a memory that holds a physical block counter including the number of erase times, a logical block counter including the number of write times, and a logical-physical conversion table; and a control unit that writes data to any physical block address. When the control unit receives a writing data instruction, the control unit updates the number of write times corresponding to the write destination logical block address, if the number of write times corresponding to the write destination logical block address is large, the control unit allocates to the write destination logical block address a physical block address with the number of erase times which is small among spare blocks not allocated to the logical block addresses in the logical-physical conversion table, updates the number of erase times corresponding to the allocated physical block address, and updates the logical-physical conversion table.

Abstract translation: 存储器控制器包括：保存包括擦除次数的物理块计数器的存储器，包括写入次数的逻辑块计数器和逻辑 - 物理转换表; 以及将数据写入任何物理块地址的控制单元。 当控制单元接收到写入数据指令时，如果与写入目的地逻辑块地址相对应的写入次数较大，则控制单元更新与写入目的地逻辑块地址相对应的写入次数，控制单元分配 写入目的地逻辑块以不分配给逻辑 - 物理转换表中的逻辑块地址的备用块中具有小的擦除次数的物理块地址来更新与分配的物理块地址相对应的擦除次数 ，并更新逻辑 - 物理转换表。

公开(公告)号：US20190335062A1

公开(公告)日：2019-10-31

申请号：US16379124

申请日：2019-04-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hirokazu SOU ,  Toshiyuki HONDA ,  Shigekazu KOGITA ,  Masato SUTO

IPC: H04N1/44 ,  G06F12/10 ,  G06F21/60 ,  H04N1/32

Abstract: A memory controller includes a data discard controller, calculates a physical address of discard object data designated by a logical address by a host device, and registers the calculated physical address as discard object data information. With respect to a predetermined command from the host device, the data discard controller outputs current discard object data information to the host device. When no command is received from the host device, the data discard controller physically erases the discard object data on the basis of the discard object data information.

公开(公告)号：US20160283150A1

公开(公告)日：2016-09-29

申请号：US15079959

申请日：2016-03-24

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shigekazu KOGITA ,  Hirokazu SO ,  Toshiyuki HONDA

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679 ,  G06F11/00 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3431

Abstract: A non-volatile storage device of the present disclosure includes non-volatile memory configured to have a plurality of areas for storing data, and a memory controller configured to write the data to the non-volatile memory and to read the data from the non-volatile memory. The memory controller includes a memory interface (I/F) connected to the non-volatile memory, a threshold calculator calculating a threshold for the number of error bits of the data based on a storage condition in the case of storing the data in the non-volatile memory without power, and a refresh controller determining whether refresh processing of the data is necessary, based on the threshold and the number of error bits of the data, and executing the refresh processing of the data if the refresh processing of the data is necessary.

Abstract translation: 本公开的非易失性存储装置包括被配置为具有用于存储数据的多个区域的非易失性存储器，以及配置为将数据写入非易失性存储器并从非易失性存储器读取数据的存储器控​​制器， 易失性存储器 存储器控制器包括连接到非易失性存储器的存储器接口（I / F），阈值计算器基于在非数据存储器中存储数据的情况下的存储条件来计算数据的错误位数的阈值 并且刷新控制器基于阈值和数据的错误位数确定是否需要数据的刷新处理，并且如果数据的刷新处理是数据的刷新处理，则执行数据的刷新处理 必要。