公开(公告)号：US20190391762A1

公开(公告)日：2019-12-26

申请号：US16441606

申请日：2019-06-14

Applicant: Panasonic Intellectual Property Management Co. Ltd.

Inventor： Shigekazu KOGITA ,  Toshiyuki HONDA ,  Hirokazu SO ,  Masato SUTO

IPC: G06F3/06 ,  G06F12/10 ,  G06F12/02

Abstract: A memory controller includes an address converter configured to convert an address designated by a host device for writing and reading into a physical address of a non-volatile memory, and an invalid-area manager configured to manage an invalid area of the non-volatile memory, the address converter making no reference to the invalid area, and, upon receipt of an invalid-data read command from the host device, data in the invalid area, managed by the invalid-area manager, of the non-volatile memory is output to the host device.

公开(公告)号：US20160179613A1

公开(公告)日：2016-06-23

申请号：US14968830

申请日：2015-12-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masato SUTO

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/05

CPC classification number: G06F11/1048 ,  H03M13/05

Abstract: A nonvolatile memory apparatus is provided with a nonvolatile memory including a plurality of blocks each being a recording area of the data and a unit of erasing of the data, and a controller for controlling writing or reading of the data to/from the nonvolatile memory. Each of the blocks includes pages each being a unit of reading of the data. The controller, when data of a first page is read in response to the data read request from the external apparatus, reads data of an other page other than the first page in a block from which the data is read, and calculates a number of errors of the data in the other page, and rewrites the data into an other block when the block from which the data is read satisfies a predetermined condition on the error based on the calculated number of errors.

Abstract translation: 非易失性存储装置具备非易失性存储器，该非易失性存储器包括多个块，每个块是数据的记录区域和数据的擦除单元;控制器，用于控制从非易失性存储器写入或读取数据。 每个块包括页面，每个页面是数据读取的单位。 当响应于来自外部设备的数据读取请求读取第一页的数据时，控制器在读取数据的块中读取除了第一页之外的另一页的数据，并计算出错误的数量 的数据，并且当读取数据的块基于计算出的错误数量满足关于错误的预定条件时，将数据重写为另一个块。

公开(公告)号：US20160179392A1

公开(公告)日：2016-06-23

申请号：US15061382

申请日：2016-03-04

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Masato SUTO

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0608 ,  G06F3/0632 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0653 ,  G06F3/0655 ,  G06F3/0679 ,  G06F11/3485 ,  G06F2201/88

Abstract: In a non-volatile memory device, a non-volatile memory has: a user data area, writing/reading data into/from the user data area being possible according to an access by an external device; and an access information storing area for storing access information indicating the access. A memory controller is connected to the non-volatile memory, and includes an access information writing unit that stores the access information in the access information storing area on an occurrence of the access. The access information includes: an access type including at least writing of data, reading of data, deletion of data, and initialization of the memory controller; a data address in the user data area, and a data size. An access information writing unit stores the access information in the access information storing area so that an order of a process executed by the memory controller according to the access can be obtained.

Abstract translation: 在非易失性存储器件中，非易失性存储器具有：用户数据区域，根据外部设备的访问，将数据写入/从用户数据区域读取数据; 以及访问信息存储区域，用于存储指示访问的访问信息。 存储器控制器连接到非易失性存储器，并且包括访问信息写入单元，其在访问的发生时将访问信息存储在访问信息存储区域中。 访问信息包括：至少包括数据写入，数据读取，数据删除以及存储器控制器的初始化的访问类型; 用户数据区域中的数据地址和数据大小。 访问信息写入单元将访问信息存储在访问信息存储区域中，使得可以获得由存储器控制器根据访问执行的处理的顺序。

公开(公告)号：US20190335062A1

公开(公告)日：2019-10-31

申请号：US16379124

申请日：2019-04-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hirokazu SOU ,  Toshiyuki HONDA ,  Shigekazu KOGITA ,  Masato SUTO

IPC: H04N1/44 ,  G06F12/10 ,  G06F21/60 ,  H04N1/32

Abstract: A memory controller includes a data discard controller, calculates a physical address of discard object data designated by a logical address by a host device, and registers the calculated physical address as discard object data information. With respect to a predetermined command from the host device, the data discard controller outputs current discard object data information to the host device. When no command is received from the host device, the data discard controller physically erases the discard object data on the basis of the discard object data information.

公开(公告)号：US20150220457A1

公开(公告)日：2015-08-06

申请号：US14685038

申请日：2015-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshikazu KATOH ,  Takuji MAEDA ,  Shinji INOUE ,  Masato SUTO

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F21/31 ,  G06F21/73 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/2107 ,  G09C1/00 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  H04L2209/12

Abstract: A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

Abstract translation: 密码处理装置包括：密码控制电路，用于根据转换参数数据执行明文数据的加密和密文数据的解密中的至少一个; 以及包括多个存储单元的存储单元阵列，所述多个存储单元包括：可变状态的存储单元，其中电阻值根据施加的电信号在多个可变电阻值范围之间可逆地变化 到; 以及处于初始状态的存储单元，其不改变为可变状态，除非将初始状态下的存储单元改变为可变状态的形成应力，则初始状态下的存储单元的电阻值为 在与多个可变电阻值范围不重叠的初始电阻值范围内，其中在存储单元阵列中，基于多个存储单元中的每一个是否处于初始状态来存储包括转换参数数据的数据 状态或可变状态。