公开(公告)号：US20200026670A1

公开(公告)日：2020-01-23

申请号：US16584487

申请日：2019-09-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji INOUE

IPC: G06F13/16 ,  G06F13/42

Abstract: In an information processing device serving as a PCIe system including a host device and a plurality of memory devices, one of the plurality of memory devices is defined as a master memory. The other memory devices are defined as slave memories, and are logically coupled to the master memory. The plurality of memory devices thus constitute a single virtual storage. When accessing is performed from a root complex to the plurality of memory devices constituting the single virtual storage, the root complex hands over a bus master to the master memory. The master memory receives a command regarding the accessing from the root complex, changes address information used for the accessing in the command regarding the accessing, based on a logical relationship with the slave memories, and sends changed command regarding the accessing to the slave memories.

公开(公告)号：US20200026452A1

公开(公告)日：2020-01-23

申请号：US16584767

申请日：2019-09-26

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji INOUE

IPC: G06F3/06

Abstract: A recording medium includes a nonvolatile memory having a storage region used for writing of data, and a controller configured to control the writing of data onto the storage region. The controller divides the storage region into a plurality of areas, selects one area among the plurality of areas, and uses only the one area as a data recording region. When a rewriting ratio in the one area reaches a first predetermined value, the controller switches the data recording region from the one area to another area having not yet used among the plurality of areas.

公开(公告)号：US20240028674A1

公开(公告)日：2024-01-25

申请号：US18374743

申请日：2023-09-29

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji INOUE ,  Yusuke SHIMIZU

IPC: G06F21/30 ,  G06T1/60 ,  G06T9/00 ,  G06F3/14 ,  G06F21/62

CPC classification number: G06F21/30 ,  G06T1/60 ,  G06T9/00 ,  G06F3/14 ,  G06F21/6209 ,  G06F2221/2141

Abstract: A method is provided that determines authenticity of a second recording medium mounted in a second device by using a first device mounted with a first recording medium. A non-user area of the first recording medium previously records first identification information and first algorithm data. A controller of the first recording medium causes a first display device to display a first image pattern and, after display of the first image pattern, causes a first imaging device to capture a second image pattern displayed on a second display device of the second device. The controller decodes first code data from the second image pattern and utilizes the first algorithm data to perform arithmetic that uses the first identification information and a first variable value. The controller determines the second recording medium to be authentic if the decoded first code data matches an arithmetic result.

公开(公告)号：US20220138129A1

公开(公告)日：2022-05-05

申请号：US17572904

申请日：2022-01-11

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji INOUE

IPC: G06F13/16 ,  B60R25/24 ,  B60R16/023 ,  B60R25/31 ,  B60R22/48 ,  B60R25/34 ,  G06F12/02

Abstract: The present disclosure provides an on-board storage system in which the time required for initializing a storage device is substantially shortened by devising a backend start timing. The on-board storage system includes: a storage device that has a controller, a NAND flash memory, and an interface; an electronic control unit that electronically controls a vehicle; and a sensor. The electronic control unit communicates with the storage device through the interface, the sensor transmits a detection result of the sensor to the electronic control unit, and the electronic control unit transmits a command to start initialization of the NAND flash memory to the controller when the transmitted detection result of the sensor indicates a driving-start preliminary operation.

公开(公告)号：US20220138353A1

公开(公告)日：2022-05-05

申请号：US17573827

申请日：2022-01-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji INOUE

IPC: G06F21/78 ,  G06F21/31 ,  G06F3/06

Abstract: The present disclosure provides an on-board secure storage system capable of easily and quickly detecting unauthorized access to a storage device and a failure of the storage device, and appropriately using the detection result. the on-board secure storage system includes the storage device that has a controller, a non-volatile memory and an interface, and an electronic control unit that electronically controls a vehicle. After determining that unauthorized access or a failure occurs in the non-volatile memory, the controller performs predetermined processing according to the type of the unauthorized access or failure.

公开(公告)号：US20160004646A1

公开(公告)日：2016-01-07

申请号：US14769615

申请日：2014-02-06

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Takuji MAEDA ,  Shinji INOUE ,  Yoshikazu KATOH

IPC: G06F12/14 ,  G06F12/02

CPC classification number: G06F12/1408 ,  G06F12/0238 ,  G06F21/62 ,  G06F2212/1052 ,  G06F2212/202 ,  H04L9/088 ,  H04L9/0897 ,  H04L9/14 ,  H04L2209/605

Abstract: An encryption and recording apparatus storing data, the apparatus including: a first nonvolatile memory; a second nonvolatile memory; and an encryption and decryption control unit, wherein the encryption and decryption control unit: manages an area included in the second nonvolatile memory on a per-block basis, and manages association between a block and a block-unique key using key management information stored in the first nonvolatile memory; receives the data and corresponding information associated with the data; encrypts the data, using one or more block-unique keys associated with one or more blocks included in the second nonvolatile memory and writes the data to the one or more blocks; and stores the corresponding information into the key management information, associating the corresponding information and the one or more block-unique keys.

Abstract translation: 一种存储数据的加密和记录装置，该装置包括：第一非易失性存储器; 第二非易失性存储器; 以及加密和解密控制单元，其中所述加密和解密控制单元在每个块的基础上管理包括在所述第二非易失性存储器中的区域，并且使用存储在所述第一非易失性存储器中的密钥管理信息来管理块和块唯一密钥之间的关联 第一个非易失性存储器; 接收与数据相关联的数据和对应信息; 使用与包括在第二非易失性存储器中的一个或多个块相关联的一个或多个块唯一密钥来加密数据，并将数据写入到一个或多个块; 并将对应的信息存储到密钥管理信息中，将相应的信息与一个或多个块唯一密钥相关联。

公开(公告)号：US20150220457A1

公开(公告)日：2015-08-06

申请号：US14685038

申请日：2015-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Yoshikazu KATOH ,  Takuji MAEDA ,  Shinji INOUE ,  Masato SUTO

IPC: G06F12/14

CPC classification number: G06F12/1408 ,  G06F21/31 ,  G06F21/73 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/2107 ,  G09C1/00 ,  G11C7/1006 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0083 ,  H04L2209/12

Abstract: A cryptographic processing device comprises a cipher control circuit operative to execute at least one of encryption of plaintext data and decryption of ciphertext data on the basis of conversion parameter data; and a memory cell array that includes a plurality of memory cells, the plurality of memory cells including: a memory cell in a variable state, in which a resistance value reversibly changes between a plurality of changeable resistance value ranges in accordance with an electric signal applied thereto; and a memory cell in an initial state, which does not change to the variable state unless a forming stress for changing the memory cell in the initial state to the variable state is applied thereto, a resistance value of the memory cell in the initial state being within an initial resistance value range which does not overlap with the plurality of changeable resistance value ranges, wherein in the memory cell array, data including the conversion parameter data is stored on the basis of whether each of the plurality of memory cells is in the initial state or the variable state.

Abstract translation: 密码处理装置包括：密码控制电路，用于根据转换参数数据执行明文数据的加密和密文数据的解密中的至少一个; 以及包括多个存储单元的存储单元阵列，所述多个存储单元包括：可变状态的存储单元，其中电阻值根据施加的电信号在多个可变电阻值范围之间可逆地变化 到; 以及处于初始状态的存储单元，其不改变为可变状态，除非将初始状态下的存储单元改变为可变状态的形成应力，则初始状态下的存储单元的电阻值为 在与多个可变电阻值范围不重叠的初始电阻值范围内，其中在存储单元阵列中，基于多个存储单元中的每一个是否处于初始状态来存储包括转换参数数据的数据 状态或可变状态。

公开(公告)号：US20210240396A1

公开(公告)日：2021-08-05

申请号：US17235819

申请日：2021-04-20

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shinji INOUE ,  Takuji MAEDA

IPC: G06F3/06 ,  G06F12/1009 ,  G06F12/0806 ,  G06F21/44

Abstract: A storage device is connected to a host device. The storage device includes a non-volatile memory, a logical area manager that divides the non-volatile memory into a plurality of logical areas, an area information storage that stores information regarding the plurality of logical areas, an access pattern manager that manages access patterns that are designated by the host device and each correspond to a corresponding one of the plurality of logical areas, an access pattern storage that stores information regarding the access patterns, an access pattern processing manager that selects, when any one of the plurality of logical areas is accessed from the host device, an access pattern corresponding to the any one of the plurality of logical areas accessed from the information, and an access processing management and execution unit that performs processing on the non-volatile memory based on the access pattern and transfers data to the host device.