公开(公告)号：US20210257033A1

公开(公告)日：2021-08-19

申请号：US16805848

申请日：2020-03-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Bo-Jing Lin ,  Yu-Chiang Liao

IPC: G11C16/32 ,  H03L7/081 ,  H03L7/093 ,  H04L7/00

Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.

公开(公告)号：US11101003B1

公开(公告)日：2021-08-24

申请号：US16805848

申请日：2020-03-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Bo-Jing Lin ,  Yu-Chiang Liao

IPC: G11C29/02 ,  G11C16/32 ,  H04L7/00 ,  H03L7/093 ,  H03L7/081

Abstract: A clock and data recovery circuit, a memory storage device and a signal adjustment method are disclosed. The method includes: detecting a phase difference between a first signal and a clock signal; generating a vote signal according to the phase difference and a first clock frequency; sequentially outputting a plurality of adjustment signals according to the vote signal and a second clock frequency, wherein the first clock frequency is different from the second clock frequency; and generating the clock signal according to the sequentially output adjustment signals.

公开(公告)号：US10965438B1

公开(公告)日：2021-03-30

申请号：US16779666

申请日：2020-02-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Yang Sun ,  Sheng-Wen Chen ,  Yen-Po Lin ,  Bo-Jing Lin ,  Po-Min Cheng

IPC: H04L7/00 ,  H04L25/03 ,  H03L7/085 ,  H03L7/099

Abstract: A signal receiving circuit, a memory storage device and a signal receiving method are provided. The signal receiving circuit includes an equalizer module, a clock and data recovery (CDR) circuit and a controller. The equalizer module is configured to receive a first signal and compensate the first signal to generate a second signal. The CDR circuit is configured to perform a phase locking on the second signal. The controller is configured to open or close a signal pattern filter of the CDR circuit according to the second signal, wherein the signal pattern filter is configured to filter a signal having a specific pattern in the second signal.