公开(公告)号：US09935774B2

公开(公告)日：2018-04-03

申请号：US14954638

申请日：2015-11-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma

IPC: H04L9/32 ,  H04L29/06 ,  H04L12/40 ,  G06F21/60 ,  G06F21/85

CPC classification number: H04L9/3242 ,  G05B19/418 ,  G06F21/602 ,  G06F21/606 ,  G06F21/85 ,  H04L12/40032 ,  H04L63/06 ,  H04L63/123 ,  H04L63/1408 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and an operational mode controller connected between the security module and the CAN bus interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from the microcontroller communications interface. The operational mode controller is configured to set an operational mode for the CAN transceiver such that a CAN Flexible Data-rate (FD) frame or a corresponding CAN frame is output from the CAN bus interface. An identifier of the CAN FD frame is the same as an identifier of the corresponding CAN frame.

公开(公告)号：US09490782B2

公开(公告)日：2016-11-08

申请号：US14527865

申请日：2014-10-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: H03K3/3562 ,  H03K3/037 ,  H03K3/356 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract translation: 锁存电路基于主从交叉耦合逆变器对配置。 从电路的反相器耦合到高电压轨和低压轨，其中对于从电路逆变器对的两个反相器中的每一个，与一个电压轨的耦合通过电阻元件。 该电路设计避免了内部时钟缓冲器的需要，并且可以实现单相时钟，因此不需要内部时钟信号反相。 该电路可以实现低功耗，当输入和输出数据信号相同时，无冗余转换的动态功耗。

公开(公告)号：US20190273649A1

公开(公告)日：2019-09-05

申请号：US15910644

申请日：2018-03-02

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Hubertus Gerardus Hendrikus Vermeulen

IPC: H04L12/24 ,  B60R16/023

Abstract: A device for proactively providing fault tolerance to a vehicle network is disclosed. The device includes a first interface to collect performance data from a plurality of network components of the vehicle network and a second interface to send reconfiguration instructions to the plurality of network components. The device may also include a database for storing the collected performance data, a processor to calculate a probability of failure of a network component in the plurality of network components based on the stored performance data.

公开(公告)号：US20160098062A1

公开(公告)日：2016-04-07

申请号：US14504789

申请日：2014-10-02

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: G06F1/10

CPC classification number: G06F1/10 ,  H03K5/159 ,  H03K19/094

Abstract: Aspects of the present disclosure are directed to operating time-based circuitry. As may be implemented in connection with one or more embodiments, an apparatus and or method involved detecting timing characteristics of circuitry operating in respective clock domains, each having a semiconductor body region via which a clock signal path traverses. The respective semiconductor body regions are biased at respective bias levels that are based on the detected timing characteristics of the clock signal path that traverses the semiconductor body region being biased.

Abstract translation: 本公开的方面涉及操作基于时间的电路。 可以结合一个或多个实施例来实现，一种装置和/或方法涉及检测在相应时钟域中工作的电路的定时特性，每个时钟域具有时钟信号路径经过的半导体主体区域。 各个半导体本体区域以各自的偏置电平被偏置，这些偏置电平是基于检测到的偏移半导体主体区域的时钟信号路径的定时特性。

公开(公告)号：US20150123722A1

公开(公告)日：2015-05-07

申请号：US14527865

申请日：2014-10-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Ajay Kapoor ,  Ralf Malzahn

IPC: H03K3/3562 ,  H03K3/012

CPC classification number: H03K3/35625 ,  H03K3/012 ,  H03K3/0372 ,  H03K3/356104 ,  H03K3/356156

Abstract: A latch circuit is based on a master-slave cross-coupled inverter pair configuration. The inverters of the slave circuit are coupled to a high voltage rail and a low voltage rail, wherein for each of the two inverters of the slave circuit inverter pair, the coupling to one of the voltage rails is through a resistive element. This circuit design avoids the need for an internal clock-buffer and enables single phase clocking, and therefore does not need internal clock signal inversion. The circuit can be implemented with low power, with no dynamic power consumption for redundant transitions when the input and the output data signal is same.

Abstract translation: 锁存电路基于主从交叉耦合逆变器对配置。 从电路的反相器耦合到高电压轨和低压轨，其中对于从电路逆变器对的两个反相器中的每一个，与一个电压轨的耦合通过电阻元件。 该电路设计避免了内部时钟缓冲器的需要，并且可以实现单相时钟，因此不需要内部时钟信号反相。 该电路可以实现低功耗，当输入和输出数据信号相同时，无冗余转换的动态功耗。

公开(公告)号：US20150091627A1

公开(公告)日：2015-04-02

申请号：US14478851

申请日：2014-09-05

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Jose de Jesus Pineda De Gyvez

IPC: H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/0375 ,  H03K3/356121 ,  H03K3/356139 ,  H03K3/356156

Abstract: A sequential circuit arrangement and method are provided in which a latch input signal and a latched version of the input signal are compared to derive a difference signal. This difference signal can detect when changes in the input are not propagated to the output. A second logic gate arrangement derives an error signal from the product of difference signal and a delayed version of the difference signal. This means that normal operation of the circuit is not detected as an error—only when the latched output fails to follow the input after the normally expected delay is the error signal created. The latch element output or an inverted version of the latch element output is selected in dependence on the error signal.

Abstract translation: 提供了一种顺序电路布置和方法，其中将锁存输入信号和输入信号的锁存版本进行比较以导出差分信号。 该差分信号可以在输入的变化不被传播到输出时检测。 第二逻辑门装置从差分信号的乘积和差分信号的延迟版本中导出误差信号。 这意味着电路的正常运行不会被检测为只有当锁存的输出在正常预期的延迟是创建的误差信号之后不能跟随输入时才是错误的。 根据误差信号选择锁存元件输出或锁存元件输出的反相形式。

公开(公告)号：US10095634B2

公开(公告)日：2018-10-09

申请号：US14720132

申请日：2015-05-22

Applicant: NXP B.V.

Inventor： Vibhu Sharma

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/56 ,  H04L29/06 ,  G06F13/42 ,  H04L12/40

Abstract: Embodiments of a device and method are disclosed. In an embodiment, an IVN transceiver is disclosed. The IVN transceiver includes an IVN bus interface, a microcontroller communications interface, and a security module connected between the IVN bus interface and the microcontroller communications interface and configured to perform a security function.

公开(公告)号：US09590599B1

公开(公告)日：2017-03-07

申请号：US14879878

申请日：2015-10-09

Applicant: NXP B.V.

Inventor： Vibhu Sharma

IPC: H03K3/3562 ,  H03K3/037

CPC classification number: H03K3/0372 ,  H03K3/012 ,  H03K3/35625

Abstract: An apparatus is disclosed that includes a clock distribution circuit configured to shift a first clock signal in the first voltage domain to a second voltage domain to produce the second clock signal. The second voltage domain extends outside of the first voltage domain. A set of flip-flops operating in the first voltage domain, each including a master latch, a slave latch, and a clock node is coupled to receive the second clock signal. Each flip-flop includes a master pass transistor configured to pass a value from an input of the flip-flop to an input of the master latch when the second clock node is set to a first value. Each flip-flop also includes a master pass transistor configured to pass the value from an output of the master latch to an input of the slave latch when the second clock node is set to a second value.

Abstract translation: 公开了一种装置，其包括时钟分配电路，其被配置为将第一电压域中的第一时钟信号移位到第二电压域以产生第二时钟信号。 第二电压域延伸到第一电压域的外部。 在第一电压域中操作的一组触发器，每个触发器包括主锁存器，从锁存器和时钟节点，以接收第二时钟信号。 每个触发器包括主通道晶体管，其被配置为当第二时钟节点被设置为第一值时将值从触发器的输入传递到主锁存器的输入。 每个触发器还包括主通道晶体管，其被配置为当第二时钟节点被设置为第二值时将该值从主锁存器的输出传递到从锁存器的输入。

公开(公告)号：US20160344703A1

公开(公告)日：2016-11-24

申请号：US14812909

申请日：2015-07-29

Applicant: NXP B.V.

Inventor： Vibhu Sharma ,  Matthias Berthold Muth

IPC: H04L29/06 ,  G06F13/42

CPC classification number: H04L63/0428 ,  G06F13/4282 ,  G06F21/567 ,  G06F21/602 ,  G06F21/606 ,  G06F21/85 ,  H04L12/40006 ,  H04L12/40032 ,  H04L63/1408 ,  H04L63/168 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a Controller Area Network (CAN) device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and a shield device connected between the CAN bus interface and the microcontroller communications interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from a Serial Peripheral Interface (SPI) interface of the microcontroller communications interface. The shield device is configured to direct CAN Flexible Data-rate (FD) traffic received from the CAN bus interface to the security module.

Abstract translation: 公开了一种装置和方法的实施例。 在一个实施例中，控制器局域网（CAN）设备包括连接在CAN收发器的CAN总线接口和CAN收发器的微控制器通信接口之间的安全模块以及连接在CAN总线接口和微控制器通信接口之间的屏蔽设备 。 安全模块被配置为对从CAN总线接口或从微控制器通信接口的串行外设接口（SPI）接口接收的数据业务执行安全功能。 屏蔽设备被配置为将从CAN总线接口接收到的CAN灵活数据速率（FD）业务指向安全模块。

公开(公告)号：US20160344552A1

公开(公告)日：2016-11-24

申请号：US14954638

申请日：2015-11-30

Applicant: NXP B.V.

Inventor： Vibhu Sharma

IPC: H04L9/32 ,  H04L29/06

CPC classification number: H04L9/3242 ,  G05B19/418 ,  G06F21/602 ,  G06F21/606 ,  G06F21/85 ,  H04L12/40032 ,  H04L63/06 ,  H04L63/123 ,  H04L63/1408 ,  H04L2012/40215 ,  H04L2012/40273

Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device includes a security module connected between a CAN bus interface of a CAN transceiver and a microcontroller communications interface of the CAN transceiver and an operational mode controller connected between the security module and the CAN bus interface. The security module is configured to perform a security function on data traffic received from the CAN bus interface or from the microcontroller communications interface. The operational mode controller is configured to set an operational mode for the CAN transceiver such that a CAN Flexible Data-rate (FD) frame or a corresponding CAN frame is output from the CAN bus interface. An identifier of the CAN FD frame is the same as an identifier of the corresponding CAN frame.

Abstract translation: 公开了一种装置和方法的实施例。 在一个实施例中，CAN设备包括连接在CAN收发器的CAN总线接口和CAN收发器的微控制器通信接口之间的安全模块以及连接在安全模块和CAN总线接口之间的操作模式控制器。 安全模块被配置为对从CAN总线接口或从微控制器通信接口接收的数据业务执行安全功能。 操作模式控制器被配置为设置CAN收发器的操作模式，使CAN CAN数据速率（FD）帧或相应的CAN帧从CAN总线接口输出。 CAN FD帧的标识符与对应的CAN帧的标识符相同。