公开(公告)号：US09977699B2

公开(公告)日：2018-05-22

申请号：US14936686

申请日：2015-11-10

Applicant: MediaTek Inc.

Inventor： Jia-Ming Chen ,  Hung-Lin Chou ,  Ya-Ting Chang ,  Shih-Yen Chiu ,  Chia-Hao Hsu ,  Yu-Ming Lin ,  Wan-Ching Huang ,  Jen-Chieh Yang ,  Pi-Cheng Hsiao

IPC: G06F9/46 ,  G06F9/50 ,  G06F1/32

CPC classification number: G06F9/5094 ,  G06F1/3206 ,  G06F1/3287 ,  G06F1/329 ,  G06F2209/505 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: A multi-cluster system having processor cores of different energy efficiency characteristics is configured to operate with high efficiency such that performance and power requirements can be satisfied. The system includes multiple processor cores in a hierarchy of groups. The hierarchy of groups includes: multiple level-1 groups, each level-1 group including one or more of processor cores having identical energy efficiency characteristics, and each level-1 group configured to be assigned tasks by a level-1 scheduler; one or more level-2 groups, each level-2 group including respective level-1 groups, the processor cores in different level-1 groups of the same level-2 group having different energy efficiency characteristics, and each level-2 group configured to be assigned tasks by a respective level-2 scheduler; and a level-3 group including the one or more level-2 groups and configured to be assigned tasks by a level-3 scheduler.

公开(公告)号：US20170160782A1

公开(公告)日：2017-06-08

申请号：US15236247

申请日：2016-08-12

Applicant: MediaTek Inc.

Inventor： Ya-Ting Chang ,  Jia-Ming Chen ,  Nicholas Ching Hui Tang ,  Pi-Cheng Hsiao

IPC: G06F1/32

CPC classification number: G06F1/3203 ,  G06F1/3206 ,  G06F1/325 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/171

Abstract: A multicore processor system utilizes a power manager for improving power consumption. The system includes multiple processing units and multiple power sources. Each power source is connected to two or more processing units. A condition for activating a processing unit is detected. In response to the detected condition, the power manager identifies a power source that is connected to inactive processing units only. The power manager then activates a target processing unit among the inactive processing units connected to the identified power source.

公开(公告)号：US20180143903A1

公开(公告)日：2018-05-24

申请号：US15620794

申请日：2017-06-12

Applicant: MediaTek Inc.

Inventor： Ming-Ju Wu ,  Chien-Hung Lin ,  Chia-Hao Hsu ,  Pi-Cheng Hsiao ,  Shao-Yu Wang

IPC: G06F12/0804 ,  G06F12/0815 ,  G06F12/121

CPC classification number: G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0833 ,  G06F12/12 ,  G06F12/121 ,  G06F2212/60 ,  G06F2212/621

Abstract: A multi-cluster, multi-processor computing system performs a cache flushing method. The method begins with a cache maintenance hardware engine receiving a request from a processor to flush cache contents to a memory. In response, the cache maintenance hardware engine generates commands to flush the cache contents to thereby remove workload of generating the commands from the processors. The commands are issued to the clusters, with each command specifying a physical address that identifies a cache line to be flushed.

公开(公告)号：US20160314024A1

公开(公告)日：2016-10-27

申请号：US15098876

申请日：2016-04-14

Applicant: MediaTek Inc.

Inventor： Ya-Ting Chang ,  Ming-Ju Wu ,  Pi-Cheng Chen ,  Jia-Ming Chen ,  Chung-Ho Chang ,  Pi-Cheng Hsiao ,  Hung-Lin Chou ,  Shih-Yen Chiu

IPC: G06F9/50

CPC classification number: G06F9/5088 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/5022 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D50/20

Abstract: A computing system supports a clearance mode for its processor cores. The computing system can transition a target processor core from an active mode into a clearance mode according to a system policy. The system policy determines the number of processor cores to be in the active mode. The transitioning into the clearance mode includes the operations of migrating work from the target processor core to one or more other processor cores in the active mode in the computing system; and removing the target processor core from a scheduling configuration of the computing system to prevent task assignment to the target processor core. When the target processor core is in the clearance mode, the target processor core is maintained in an online idle state in which the target processor core performs no work.

Abstract translation: 计算系统支持其处理器核心的清除模式。 计算系统可以根据系统策略将目标处理器核心从活动模式转换到清除模式。 系统策略确定处于活动模式的处理器核心数。 过渡到清除模式包括在计算系统中将工作从目标处理器核心迁移到活动模式中的一个或多个其他处理器核心的操作; 以及从所述计算系统的调度配置中移除所述目标处理器核以防止对所述目标处理器核心的任务分配。 当目标处理器核心处于清除模式时，目标处理器核心维持在目标处理器核心不工作的在线空闲状态。

公开(公告)号：US20170023997A1

公开(公告)日：2017-01-26

申请号：US15071780

申请日：2016-03-16

Applicant: MediaTek Inc.

Inventor： Jia-Ming Chen ,  Hung-Lin Chou ,  Pi-Cheng Hsiao ,  Yen-Lin Lee ,  Ya-Ting Chang ,  Jih-Ming Hsu

IPC: G06F1/32 ,  G06F9/50 ,  G06F1/26

CPC classification number: G06F1/3234 ,  G06F1/263 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/5094 ,  Y02D10/171

Abstract: A switch interconnect is dynamically controlled at runtime to connect power sources to processing units in a multiprocessor system. Each power source is shareable by the processing units and each processing unit has a required voltage for processing a workload. When a system condition is detected at runtime, the switch interconnect is controlled to change a connection between at least one processing unit and a shared power source to maximize power efficiency. The shared power source is one of the power sources that supports multiple processing units having different required voltages.

Abstract translation: 交换机互连在运行时动态控制，以将电源连接到多处理器系统中的处理单元。 每个电源可由处理单元共享，并且每个处理单元具有用于处理工作负载的所需电压。 当在运行时检测到系统条件时，控制开关互连以改变至少一个处理单元和共享电源之间的连接以最大化功率效率。 共享电源是支持具有不同所需电压的多个处理单元的电源之一。

公开(公告)号：US20170300427A1

公开(公告)日：2017-10-19

申请号：US15487402

申请日：2017-04-13

Applicant: MEDIATEK INC.

Inventor： Chien-Hung Lin ,  Ming-Ju Wu ,  Wei-Hao Chiao ,  Kun-Geng Lee ,  Shun-Chieh Chang ,  Ming-Ku Chang ,  Chia-Hao Hsu ,  Pi-Cheng Hsiao

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/128 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0862 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/602 ,  G06F2212/621

Abstract: A multi-processor system with cache sharing has a plurality of processor sub-systems and a cache coherence interconnect circuit. The processor sub-systems have a first processor sub-system and a second processor sub-system. The first processor sub-system includes at least one first processor and a first cache coupled to the at least one first processor. The second processor sub-system includes at least one second processor and a second cache coupled to the at least one second processor. The cache coherence interconnect circuit is coupled to the processor sub-systems, and used to obtain a cache line data from an evicted cache line in the first cache, and transfer the obtained cache line data to the second cache for storage.

公开(公告)号：US10031573B2

公开(公告)日：2018-07-24

申请号：US14931923

申请日：2015-11-04

Applicant: MediaTek Inc.

Inventor： Jia-Ming Chen ,  Hung-Lin Chou ,  Pi-Cheng Hsiao ,  Ya-Ting Chang ,  Yun-Ching Li ,  Yu-Ming Lin

IPC: G06F9/46 ,  G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/324 ,  G06F9/4812 ,  G06F9/5088 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D50/20

Abstract: Energy efficiency is managed in a multi-cluster system. The system detects an event in which a current operating frequency of an active cluster enters or crosses any of one or more predetermined frequency spots of the active cluster, wherein the active cluster includes one or more first processor cores. When the event is detected, the system performs the following steps: (1) identifying a target cluster including one or more second processor cores, wherein the each first processor core in the first cluster and each second processor core in the second cluster have different energy efficiency characteristics; (2) activating at least one second processor core in the second cluster; (3) determining whether to migrate one or more interrupt requests from the first cluster to the second cluster; and (4) determining whether to deactivate at least one first processor core of the active cluster based on a performance and power requirement.