公开(公告)号：US11227846B2

公开(公告)日：2022-01-18

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20200243462A1

公开(公告)日：2020-07-30

申请号：US16742850

申请日：2020-01-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/22 ,  H01Q1/02

Abstract: A semiconductor package includes a base having an upper surface and a lower surface opposite to the upper surface. An antenna array structure is embedded at the upper surface of the base. An IC die is mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation. Solder ball pads are disposed on the lower surface of the base and arranged around the IC die. The semiconductor package further includes a metal thermal interface layer having a backside metal layer that is in direct contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US11705413B2

公开(公告)日：2023-07-18

申请号：US17549901

申请日：2021-12-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/3672 ,  H01L23/3733 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/02 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/0103 ,  H01L2924/014 ,  H01L2924/0105 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/18161

Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US09184107B2

公开(公告)日：2015-11-10

申请号：US14585575

申请日：2014-12-30

Applicant: MediaTek Inc.

Inventor： Tai-Yu Chen ,  Chung-Fa Lee ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/373 ,  H01L23/36 ,  H01L23/433 ,  H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00

CPC classification number: H01L23/3736 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/33 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/33181 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board, having a first cross sectional dimension; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; an encapsulant layer, formed over the circuit board, covering the semiconductor chip and surrounding the spacer; a heat spreading layer, formed over the encapsulant layer and the spacer; and a plurality of solder balls, formed over the second surface of the circuit board, wherein a ratio between the first cross sectional dimension and the second cross sectional dimension is about 1:2-1:6.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上，具有第一横截面尺寸; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在电路板上的密封剂层，覆盖半导体芯片并围绕间隔物; 形成在密封剂层和间隔物上的散热层; 以及形成在电路板的第二表面上的多个焊球，其中第一横截面尺寸和第二横截面尺寸之间的比率为约1：2-1：6。

公开(公告)号：US11967570B2

公开(公告)日：2024-04-23

申请号：US17687350

申请日：2022-03-04

Applicant: MediaTek Inc.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01Q1/02 ,  H01Q1/22

CPC classification number: H01L23/66 ,  H01L23/3672 ,  H01L23/3733 ,  H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01Q1/02 ,  H01Q1/2283 ,  H01L2223/6677 ,  H01L2224/16227 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01083 ,  H01L2924/014 ,  H01L2924/18161

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US20220285297A1

公开(公告)日：2022-09-08

申请号：US17687350

申请日：2022-03-04

Applicant: MediaTek Inc.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US11302657B2

公开(公告)日：2022-04-12

申请号：US16802576

申请日：2020-02-27

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L27/14 ,  H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US20220102297A1

公开(公告)日：2022-03-31

申请号：US17549901

申请日：2021-12-14

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00 ,  H01Q1/02 ,  H01Q1/22

Abstract: A semiconductor package including a base comprising an upper surface and a lower surface that is opposite to the upper surface; a radio-frequency (RF) module embedded near the upper surface of the base; an integrated circuit (IC) die mounted on the lower surface of the base in a flip-chip manner so that a backside of the IC die is available for heat dissipation; a plurality of conductive structures disposed on the lower surface of the base and arranged around the IC die; and a metal thermal interface layer comprising a backside metal layer that is in contact with the backside of the IC die, and a solder paste conformally printed on the backside metal layer.

公开(公告)号：US20200243464A1

公开(公告)日：2020-07-30

申请号：US16802576

申请日：2020-02-27

Applicant: MEDIATEK INC.

Inventor： Chia-Hao Hsu ,  Tai-Yu Chen ,  Shiann-Tsong Tsai ,  Hsing-Chih Liu ,  Yao-Pang Hsu ,  Chi-Yuan Chen ,  Chung-Fa Lee

IPC: H01L23/66 ,  H01Q1/02 ,  H01Q1/22 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498 ,  H01L23/373

Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.

公开(公告)号：US09252068B2

公开(公告)日：2016-02-02

申请号：US14611364

申请日：2015-02-02

Applicant: MediaTek Inc.

Inventor： Tai-Yu Chen ,  Chung-Fa Lee ,  Wen-Sung Hsu ,  Shih-Chin Lin

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/36 ,  H01L23/433 ,  H01L23/498 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/3675 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3736 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/29 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/04042 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/33181 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/351 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/83 ,  H01L2224/85

Abstract: A semiconductor package with reduced warpage problem is provided, including: a circuit board, having opposing first and second surfaces; a semiconductor chip, formed over a center portion of the first surface of the circuit board; a spacer, formed over a center portion of the semiconductor chip, having a second cross sectional dimension less than that of the first cross sectional dimension; a non-planar shaped heat spreading layer, formed over the spacer; an encapsulant layer, formed, over the circuit board, filling spaces between the non-planar shaped heat spreading layer and the circuit board; and a plurality of solder balls, formed over the second surface of the circuit board.

Abstract translation: 提供一种具有降低翘曲问题的半导体封装，包括：具有相对的第一和第二表面的电路板; 半导体芯片，形成在电路板的第一表面的中心部分上; 形成在所述半导体芯片的中心部分上的间隔物，具有小于所述第一横截面尺寸的第二截面尺寸; 形成在间隔物上的非平面形散热层; 形成在所述电路板上的密封剂层，在所述非平面形散热层与所述电路板之间填充空间; 以及形成在电路板的第二表面上的多个焊球。