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1.发明授权公开(公告)号：US09883591B2
公开(公告)日：2018-01-30
申请号：US15431781
申请日：2017-02-14
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
IPC: H05K1/11 , H01L23/00 , H01L23/498 , H05K1/18 , H05K1/05
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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公开(公告)号：US20160143140A1
公开(公告)日：2016-05-19
申请号：US14860718
申请日：2015-09-22
Applicant: Mediatek Inc.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
Abstract translation: 印刷电路板包括至少包括内部导电层和层压芯上的堆积层的叠层芯。 堆积层包括顶部导电层。 多个微孔设置在积层层中以将顶部导电层与内部导电层电连接。 电源/接地球垫阵列设置在顶部导电层中。 电源/接地球垫阵列包括排列成具有固定球垫间距P的阵列的功率球垫和接地球垫。电源/接地球垫阵列包括仅由一个接地球组成的4球垫单元区域 垫和三个电源球垫，或仅由一个电源球垫和三个地球垫组成。 四球垫单位面积为矩形，尺寸约为2P×2P。
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公开(公告)号：US09131602B2
公开(公告)日：2015-09-08
申请号：US13747738
申请日：2013-01-23
Applicant: MediaTek Inc.
Inventor： Sheng-Ming Chang , Shih-Chieh Lin , Nan-Cheng Chen
CPC classification number: H05K1/0219 , H05K1/0218 , H05K1/025 , H05K1/0298 , H05K1/114 , H05K1/115 , H05K2201/0723 , H05K2201/09672 , H05K2201/09709 , H05K2201/10522 , H05K2201/10674
Abstract: The invention provides a printed circuit board for mobile platforms. An exemplary embodiment of the printed circuit board for mobile platforms includes a core substrate having a first side. A ground plane covers the first side. A first insulating layer covers the ground plane. A plurality of first signal traces and a plurality of first ground traces are alternatively arranged on the first insulating layer. A second insulating layer connects to the first insulating layer. A plurality of second signal traces separated from each other is disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto.
Abstract translation: 本发明提供一种用于移动平台的印刷电路板。 用于移动平台的印刷电路板的示例性实施例包括具有第一侧的芯基板。 地平面覆盖第一面。 第一绝缘层覆盖接地层。 多个第一信号迹线和多个第一接地迹线交替地布置在第一绝缘层上。 第二绝缘层连接到第一绝缘层。 彼此分离的多个第二信号迹线设置在第二绝缘层上，其中第二信号迹线直接设置在第一信号迹线和与其相邻的第一接地迹线之间的空间上。
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公开(公告)号：US09158880B2
公开(公告)日：2015-10-13
申请号：US14043197
申请日：2013-10-01
Applicant: MediaTek Inc.
Inventor： Fu-Kang Pan , Nan-Cheng Chen , Shih-Chieh Lin , Hui-Chi Tang , Ying Liu , Yang Liu
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F2217/12 , G06F2217/38 , G06F2217/40
Abstract: A layout method for a printed circuit board (PCB) is provided. A memory type of a dynamic random access memory (DRAM) to be mounted on the PCB is obtained. A module group is obtained from a database according to the memory type of the DRAM, wherein the module group includes a plurality of routing modules. A plurality of PCB parameters are obtained. A specific routing module is selected from the module group according to the PCB parameters. The specific routing module is implemented into a layout design of the PCB. The specific routing module includes layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.
Abstract translation: 提供了印刷电路板（PCB）的布局方法。 获得要安装在PCB上的动态随机存取存储器（DRAM）的存储器类型。 根据DRAM的存储器类型从数据库获得模块组，其中模块组包括多个路由模块。 获得多个PCB参数。 根据PCB参数从模块组中选择一个特定的路由模块。 具体的路由模块被实现为PCB的布局设计。 特定路由模块包括关于主芯片，存储芯片以及主芯片和存储芯片之间的路由配置的布局信息。
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公开(公告)号：US09674941B2
公开(公告)日：2017-06-06
申请号：US14816204
申请日：2015-08-03
Applicant: MediaTek Inc.
Inventor： Sheng-Ming Chang , Shih-Chieh Lin , Nan-Cheng Chen
CPC classification number: H05K1/0219 , H05K1/0218 , H05K1/025 , H05K1/0298 , H05K1/114 , H05K1/115 , H05K2201/0723 , H05K2201/09672 , H05K2201/09709 , H05K2201/10522 , H05K2201/10674
Abstract: A printed circuit board for mobile platforms includes a core substrate having a first side, a ground plane covering on the first side, a first insulating layer covering the ground plane, and a plurality of first signal traces and a plurality of first ground traces, alternatively arranged on the first insulating layer, a second insulating layer connecting to the first insulating layer, and a plurality of second signal traces separated from each other, disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto, wherein coverage of the ground plane is corresponding to disposition of the first signal trace, the first ground trace, the second signal trace and the second ground trace.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20170156208A1
公开(公告)日：2017-06-01
申请号：US15431781
申请日：2017-02-14
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
IPC: H05K1/11 , H01L23/00 , H01L23/498 , H05K1/18 , H05K1/05
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A microelectronic system includes a printed circuit board and a semiconductor package mounted on the printed circuit board. The printed circuit board includes a laminated core having an internal conductive layer and a build-up layer. The build-up layer includes a top conductive layer. Microvias are disposed in the build-up layer to connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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公开(公告)号：US09609749B2
公开(公告)日：2017-03-28
申请号：US14860718
申请日：2015-09-22
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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8.发明授权公开(公告)号：US10194530B2
公开(公告)日：2019-01-29
申请号：US15847852
申请日：2017-12-19
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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9.发明申请公开(公告)号：US20180116051A1
公开(公告)日：2018-04-26
申请号：US15847852
申请日：2017-12-19
Applicant: MEDIATEK INC.
Inventor： Sheng-Ming Chang , Chia-Hui Liu , Shih-Chieh Lin , Chun-Ping Chen
CPC classification number: H05K1/115 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L23/49838 , H01L23/50 , H01L24/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2924/15311 , H01L2924/181 , H05K1/0262 , H05K1/0298 , H05K1/05 , H05K1/111 , H05K1/114 , H05K1/181 , H05K2201/09227 , H05K2201/095 , H05K2201/09509 , H05K2201/10378 , H05K2201/10674 , H05K2201/10734 , H01L2924/00012 , H01L2924/00
Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.
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公开(公告)号：US09846756B2
公开(公告)日：2017-12-19
申请号：US14843113
申请日：2015-09-02
Applicant: MediaTek Inc
Inventor： Fu-Kang Pan , Nan-Cheng Chen , Shih-Chieh Lin , Hui-Chi Tang , Ying Liu , Yang Liu , Ching-Chih Li
IPC: G06F17/50
CPC classification number: G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F2217/12 , G06F2217/38 , G06F2217/40
Abstract: A layout method for a printed circuit board (PCB) is provided. The method obtains a memory type of a dynamic random access memory (DRAM) to be mounted on the PCB, obtains a module group from a database according to the memory type of the DRAM, wherein the module group comprises a plurality of routing modules, obtains a plurality of PCB parameters, selects a specific routing module from the module group according to the PCB parameters, and implements the specific routing module into a layout design for PCB fabrication. The specific routing module comprises layout information regarding a main chip, a memory chip and a routing configuration between the main chip and the memory chip.
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