公开(公告)号：US20190098747A1

公开(公告)日：2019-03-28

申请号：US16114669

申请日：2018-08-28

Applicant: MEDIATEK INC.

Inventor： Duen-Yi HO ,  Hung-Chuan CHEN ,  Shang-Pin CHEN

IPC: H05K1/02 ,  H01L23/00 ,  G06F13/40 ,  H01L23/498

Abstract: A semiconductor device includes a substrate, a die and multiple conductive traces. The die is mounted on the substrate. The conductive traces are routed on the substrate and connected to the die. The conductive traces at least include a plurality of first conductive traces and a plurality of second conductive traces. The second conductive traces are coupled to a predetermined voltage for providing a shielding pattern. The first conductive traces and the second conductive traces are disposed on the substrate in a substantially interlaced pattern.

公开(公告)号：US20180204610A1

公开(公告)日：2018-07-19

申请号：US15862884

申请日：2018-01-05

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Ching-Yeh HSUAN ,  Shang-Pin CHEN

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4093

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/1093 ,  G11C11/408 ,  G11C11/4093 ,  G11C2207/2254

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.

公开(公告)号：US20180293026A1

公开(公告)日：2018-10-11

申请号：US15935200

申请日：2018-03-26

Applicant: MEDIATEK INC.

Inventor： Bo-Wei HSIEH ,  Chia-Yu CHAN ,  Shang-Pin CHEN

IPC: G06F3/06

Abstract: A memory system includes a memory controller, a first memory device and a second memory device. The memory controller issues a first clock signal and a second clock signal. The memory controller transmits or receives a data signal. The first memory device receives the first clock signal and the second clock signal. The second memory device receives the first dock signal and the second clock signal. If a first mode register of the first memory device is in a first single-ended mode and a second mode register of the second memory device is in a second single-ended mode, the first memory device transmits or receives the data signal according to the first dock signal, and the second memory device transmits or receives the data signal according to the second clock signal.

公开(公告)号：US20170125363A1

公开(公告)日：2017-05-04

申请号：US15408683

申请日：2017-01-18

Applicant: MEDIATEK INC.

Inventor： Chun-Wei CHANG ,  Shang-Pin CHEN

IPC: H01L23/66 ,  H01L25/065 ,  G06F13/40 ,  H01L23/538 ,  H01L23/552 ,  H05K1/02 ,  H05K1/18

CPC classification number: H01L23/66 ,  G06F13/4072 ,  H01L23/5386 ,  H01L23/552 ,  H01L24/16 ,  H01L25/0655 ,  H01L27/12 ,  H01L2223/6688 ,  H01L2224/16227 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/3025 ,  H04B3/32 ,  H05K1/0216 ,  H05K1/0218 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/181 ,  H05K3/46 ,  H05K2201/09972 ,  H05K2201/10159 ,  H05K2201/10318 ,  H05K2201/10522

Abstract: An integrated circuit is provided. The integrated circuit includes a control circuitry, a plurality of pins coupled to a plurality of conductive traces of a printed circuit board (PCB), and a plurality of driving units coupled to the pins. The control circuitry provides a plurality of control signals according to data to be transmitted. The driving units are divided into a plurality of first driving units and second driving units. According to the control signals, the first driving units provide the data to a memory device of the PCB via the corresponding pins and the corresponding conductive traces of PCB, and the second driving units provide a constant voltage to the corresponding conductive traces of PCB via the corresponding pins. The conductive traces corresponding to the second driving units are separated by the conductive traces corresponding to the first driving units on the PCB.