公开(公告)号：US20230054524A1

公开(公告)日：2023-02-23

申请号：US17678045

申请日：2022-02-23

Applicant: MEDIATEK INC.

Inventor： Chih-Wen Yang ,  Chi-Hung Chen ,  Kai-Chun Lin ,  Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/156 ,  H04N19/85 ,  H04N19/503 ,  H04N19/593 ,  H04N19/15 ,  H04N19/172

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

公开(公告)号：US11800122B2

公开(公告)日：2023-10-24

申请号：US17678045

申请日：2022-02-23

Applicant: MEDIATEK INC.

Inventor： Chih-Wen Yang ,  Chi-Hung Chen ,  Kai-Chun Lin ,  Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/42 ,  H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/156 ,  H04N19/172 ,  H04N19/503 ,  H04N19/593 ,  H04N19/15 ,  H04N19/85

CPC classification number: H04N19/423 ,  H04N19/105 ,  H04N19/127 ,  H04N19/15 ,  H04N19/156 ,  H04N19/172 ,  H04N19/503 ,  H04N19/593 ,  H04N19/85

Abstract: A video processing apparatus implemented in a chip includes an on-chip prediction buffer and a processing circuit. The on-chip prediction buffer is shared by a plurality of coding tools for prediction, and is used to store reference data. The processing circuit supports the coding tools for prediction, reads a plurality of first reference data from the on-chip prediction buffer as input data of a first coding tool that is included in the coding tools and enabled by the processing circuit, and writes output data of the first coding tool enabled by the processing circuit into the on-chip prediction buffer as a plurality of second reference data.

公开(公告)号：US12063360B2

公开(公告)日：2024-08-13

申请号：US17876567

申请日：2022-07-29

Applicant: MEDIATEK INC.

Inventor： Kai-Chun Lin ,  Chi-Hung Chen ,  Meng-Jye Hu ,  Hsiao-En Chen ,  Chih-Wen Yang ,  Chien-Wei Lin

IPC: H04N19/107 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/503 ,  H04N19/593

CPC classification number: H04N19/107 ,  H04N19/105 ,  H04N19/159 ,  H04N19/172 ,  H04N19/176 ,  H04N19/423 ,  H04N19/503 ,  H04N19/593

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.

公开(公告)号：US20230069089A1

公开(公告)日：2023-03-02

申请号：US17837071

申请日：2022-06-10

Applicant: MEDIATEK INC.

Inventor： Chien-Wei Lin ,  Meng-Jye Hu

IPC: H04N19/44 ,  H04N19/176 ,  H04N19/132 ,  H04N19/423 ,  H04N19/593 ,  H04N19/33 ,  H04N19/186 ,  H04N19/127

Abstract: A video decoder has a plurality of processing circuits, including a first processing circuit and a second processing circuit. The first processing circuit applies a first decoding process to a current coding block according to reconstructed neighbor samples, and has a local neighbor buffer for buffering the reconstructed neighbor samples used by the first decoding process. The second processing circuit applies a second decoding process to the current coding block according to at least a portion of the reconstructed neighbor samples retrieved from the local neighbor buffer, wherein the second decoding process is different from the first decoding process.

公开(公告)号：US20230064790A1

公开(公告)日：2023-03-02

申请号：US17876567

申请日：2022-07-29

Applicant: MEDIATEK INC.

Inventor： Kai-Chun Lin ,  Chi-Hung Chen ,  Meng-Jye Hu ,  Hsiao-En Chen ,  Chih-Wen Yang ,  Chien-Wei Lin

IPC: H04N19/107 ,  H04N19/176 ,  H04N19/105 ,  H04N19/423 ,  H04N19/172 ,  H04N19/593 ,  H04N19/159 ,  H04N19/503

Abstract: A prediction processing system includes a processing circuit and a reference data buffer. The processing circuit performs a first inter prediction operation upon a first prediction block in a frame to generate a first inter prediction result, and further performs a second inter prediction operation upon a second prediction block during a first period. The reference data buffer buffers a reference data derived from the first inter prediction result. The processing circuit further fetches the reference data from the reference data buffer, and performs a non-inter prediction operation according to at least the reference data during a second period, wherein the second period overlaps the first period.