公开(公告)号：US20250061077A1

公开(公告)日：2025-02-20

申请号：US18797821

申请日：2024-08-08

Applicant: Korea Advanced Institute of Science and Technology ,  Panmnesia Inc.

Inventor： Myoungsoo JUNG ,  Miryeong Kwon ,  Junhyeok JANG ,  Seungjun LEE ,  Hanjin CHOI ,  Hanyeoreum BAE

IPC: G06F13/40 ,  G06F9/48 ,  G06F13/16

Abstract: A memory expander is disclosed. The memory expander includes a memory, a memory controller configured to control the memory, a compute express link (CXL) engine configured to acquire a CXL flit from a host device connected to the memory expander and configured to acquire a calculation request for pieces of data stored in the memory by performing conversion on the CXL flit, and a domain-specific accelerator configured to perform a calculation in response to the calculation request.

公开(公告)号：US20210255942A1

公开(公告)日：2021-08-19

申请号：US17166417

申请日：2021-02-03

Applicant: MemRay Corporation ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Miryeong KWON ,  Gyuyoung PARK ,  SangWon LEE

IPC: G06F11/30 ,  G06F11/14 ,  G06F1/28 ,  G06F1/30 ,  G06F9/30 ,  G06F9/48 ,  G06F12/02

Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

公开(公告)号：US20240012684A1

公开(公告)日：2024-01-11

申请号：US18161169

申请日：2023-01-30

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Donghyun GOUK

IPC: G06F9/50 ,  G06F3/06 ,  G06F13/42

CPC classification number: G06F9/5016 ,  G06F3/0613 ,  G06F3/0659 ,  G06F3/067 ,  G06F13/4221

Abstract: Disclosed is a memory disaggregation computing system including a host server and a memory device connected through a compute express link (CXL) network, in which a computing complex of the host server is connected to a memory resource of the memory device through a CXL packet transmitted through the CXL network, and executes an application program by using the memory resource.

公开(公告)号：US20230418673A1

公开(公告)日：2023-12-28

申请号：US18166685

申请日：2023-02-09

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Junhyeok JANG ,  Miryeong KWON ,  Donghyun GOUK ,  Hanyeoreum BAE

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54

CPC classification number: G06F9/5027 ,  G06F9/54 ,  G06F9/4881

Abstract: Provided is an apparatus for accelerating a graph neural network for efficient parallel processing of massive graph datasets, including a streaming multiprocess (SM) scheduler and a computation unit, wherein the SM scheduler obtains a subgraph and an embedding table per layer, determines a number of SMs to be allocated for processing embeddings of a destination-vertex based on a feature dimension and a maximum number of threads in each of the SMs, and allocates the determined number of SMs to each of all destination-vertices included in the subgraph, and the computation unit obtains, by each of the SMs, embeddings of a destination-vertex allocated to each SM, obtains, by each SM, embeddings of at least one or more neighbor-vertices of the destination-vertex using the subgraph, and performs, by each SM, a user-designated operation using the embeddings of the destination-vertex and the embeddings of the neighbor-vertices.

公开(公告)号：US20240264957A1

公开(公告)日：2024-08-08

申请号：US18425079

申请日：2024-01-29

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Donghyun GOUK ,  Miryeong KWON

IPC: G06F13/16 ,  G06F12/02 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F12/0246 ,  G06F13/4221

Abstract: A compute express link (CXL) computing system includes a host device including a CPU that supports CXL, and a CXL storage connected to a CXL root port of the CPU based on the CXL interconnect and including a flash memory-based memory module.

公开(公告)号：US20230297500A1

公开(公告)日：2023-09-21

申请号：US17889297

申请日：2022-08-16

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Junhyeok JANG ,  Seungkwan KANG ,  Dongsuk OH ,  Myoungsoo JUNG

IPC: G06F12/02 ,  G06F12/0831 ,  G06F12/0882 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F12/0833 ,  G06F12/0882 ,  G06F12/0891

Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.

公开(公告)号：US20230221876A1

公开(公告)日：2023-07-13

申请号：US18151645

申请日：2023-01-09

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Miryeong KWON ,  Donghyun Gouk

IPC: G06F3/06

CPC classification number: G06F3/0644 ,  G06F3/061 ,  G06F3/0679

Abstract: A computational storage supporting graph machine learning acceleration includes a solid state drive (SSD) configured to store a graph data set; and a field-programmable gate array (FPGA) configured to download, to a memory, a graph machine learning model programmed in a form of a data flow graph by a host, wherein a hardware logic built in the FPGA performs access to the SSD through a peripheral component interconnect-express (PCIe) switch.

公开(公告)号：US20240303122A1

公开(公告)日：2024-09-12

申请号：US18453702

申请日：2023-08-22

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Seungkwan Kang ,  Donghyun Gouk ,  Miryeong Kwon ,  Hyunkyu CHOI ,  Junhyeok Jang

IPC: G06F9/50 ,  G06F7/36

CPC classification number: G06F9/5027 ,  G06F7/36

Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.

公开(公告)号：US20240281645A1

公开(公告)日：2024-08-22

申请号：US18450497

申请日：2023-08-16

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Myoungsoo JUNG ,  Seungkwan Kang ,  Donghyun Gouk ,  Miryeong Kwon ,  Hyunkyu Choi ,  Junhyeok Jang

IPC: G06N3/0495

CPC classification number: G06N3/0495

Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a conversion unit configured to convert an original graph in a coordinate list (COO) format into a graph in a compressed sparse row (CSR) format, a sub-graph generation unit configured to generate a sub-graph with a reduced degree of the graph in the CSR format, and an embedding table generation unit configured to generate an embedding table corresponding to the sub-graph.

公开(公告)号：US20240045588A1

公开(公告)日：2024-02-08

申请号：US18090645

申请日：2022-12-29

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Jie ZHANG ,  HANYEOREUM BAE

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0679

Abstract: An accelerator includes a processor and a hybrid memory system. The hybrid memory system includes a resistance-based non-volatile memory, a DRAM used as a cache of the resistance-based non-volatile memory, a non-volatile memory controller connected to the resistance-based non-volatile memory and configured to control the DRAM and the resistance-based non-volatile memory, a memory controller configured to process a memory request from the processor and control the DRAM, and a memory channel configured to connect the DRAM, the non-volatile memory controller, and the memory controller.