公开(公告)号：US20230297500A1

公开(公告)日：2023-09-21

申请号：US17889297

申请日：2022-08-16

Applicant: SK hynix Inc. ,  Korea Advanced Institute of Science and Technology

Inventor： Junhyeok JANG ,  Seungkwan KANG ,  Dongsuk OH ,  Myoungsoo JUNG

IPC: G06F12/02 ,  G06F12/0831 ,  G06F12/0882 ,  G06F12/0891

CPC classification number: G06F12/0246 ,  G06F12/0833 ,  G06F12/0882 ,  G06F12/0891

Abstract: A data storage device includes one or more nonvolatile memory devices each including a plurality of unit storage spaces; and an address recommending circuit configured to recommend a unit storage space among the plurality of unit storage spaces to process a write request, wherein the address recommending circuit applies feature data to a neural network to recommend the unit storage space, and wherein the feature data is generated based on request information for the write request, a target address corresponding to the write request, an address of data stored in the plurality of unit storage spaces.

公开(公告)号：US20230418673A1

公开(公告)日：2023-12-28

申请号：US18166685

申请日：2023-02-09

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Junhyeok JANG ,  Miryeong KWON ,  Donghyun GOUK ,  Hanyeoreum BAE

IPC: G06F9/50 ,  G06F9/48 ,  G06F9/54

CPC classification number: G06F9/5027 ,  G06F9/54 ,  G06F9/4881

Abstract: Provided is an apparatus for accelerating a graph neural network for efficient parallel processing of massive graph datasets, including a streaming multiprocess (SM) scheduler and a computation unit, wherein the SM scheduler obtains a subgraph and an embedding table per layer, determines a number of SMs to be allocated for processing embeddings of a destination-vertex based on a feature dimension and a maximum number of threads in each of the SMs, and allocates the determined number of SMs to each of all destination-vertices included in the subgraph, and the computation unit obtains, by each of the SMs, embeddings of a destination-vertex allocated to each SM, obtains, by each SM, embeddings of at least one or more neighbor-vertices of the destination-vertex using the subgraph, and performs, by each SM, a user-designated operation using the embeddings of the destination-vertex and the embeddings of the neighbor-vertices.

公开(公告)号：US20250061077A1

公开(公告)日：2025-02-20

申请号：US18797821

申请日：2024-08-08

Applicant: Korea Advanced Institute of Science and Technology ,  Panmnesia Inc.

Inventor： Myoungsoo JUNG ,  Miryeong Kwon ,  Junhyeok JANG ,  Seungjun LEE ,  Hanjin CHOI ,  Hanyeoreum BAE

IPC: G06F13/40 ,  G06F9/48 ,  G06F13/16

Abstract: A memory expander is disclosed. The memory expander includes a memory, a memory controller configured to control the memory, a compute express link (CXL) engine configured to acquire a CXL flit from a host device connected to the memory expander and configured to acquire a calculation request for pieces of data stored in the memory by performing conversion on the CXL flit, and a domain-specific accelerator configured to perform a calculation in response to the calculation request.