公开(公告)号：US12248814B2

公开(公告)日：2025-03-11

申请号：US18453702

申请日：2023-08-22

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo Jung ,  Seungkwan Kang ,  Donghyun Gouk ,  Miryeong Kwon ,  Hyunkyu Choi ,  Junhyeok Jang

IPC: G06F7/76 ,  G06F7/36 ,  G06F9/50

Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.

公开(公告)号：US20230007080A1

公开(公告)日：2023-01-05

申请号：US17561777

申请日：2021-12-24

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo Jung ,  Donghyun Gouk ,  Miryeong Kwon

IPC: H04L67/1097 ,  H04L69/08 ,  H04L67/60 ,  H04L67/568

Abstract: A first IP address is set to the host, and a second IP address is set to the storage card. A storage card includes a storage device and a processor for executing firmware. The host converts a first Ethernet packet including an ISP-related request and destined for the second IP address into an NVMe request according to an NVMe protocol, and transfers the NVMe request to the storage card. The firmware parses the NVMe request to perform the ISP-related request.

公开(公告)号：US20250061077A1

公开(公告)日：2025-02-20

申请号：US18797821

申请日：2024-08-08

Applicant: Korea Advanced Institute of Science and Technology ,  Panmnesia Inc.

Inventor： Myoungsoo JUNG ,  Miryeong Kwon ,  Junhyeok JANG ,  Seungjun LEE ,  Hanjin CHOI ,  Hanyeoreum BAE

IPC: G06F13/40 ,  G06F9/48 ,  G06F13/16

Abstract: A memory expander is disclosed. The memory expander includes a memory, a memory controller configured to control the memory, a compute express link (CXL) engine configured to acquire a CXL flit from a host device connected to the memory expander and configured to acquire a calculation request for pieces of data stored in the memory by performing conversion on the CXL flit, and a domain-specific accelerator configured to perform a calculation in response to the calculation request.

公开(公告)号：US11656967B2

公开(公告)日：2023-05-23

申请号：US17166417

申请日：2021-02-03

Applicant: MemRay Corporation ,  KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo Jung ,  Miryeong Kwon ,  Gyuyoung Park ,  SangWon Lee

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/14 ,  G06F12/02 ,  G06F1/30 ,  G06F9/30 ,  G06F9/48 ,  G06F1/28

CPC classification number: G06F11/3037 ,  G06F1/28 ,  G06F1/30 ,  G06F9/30047 ,  G06F9/4881 ,  G06F11/1441 ,  G06F11/3058 ,  G06F12/0238

Abstract: A method of supporting persistence of a computing device is provided. The computing device performs a stop procedure upon power failure. In the stop procedure, the computing device schedules out a running process task, stores a state of the process task to a process control block of a memory module including a non-volatile memory, flushes a cache for the processor, and flushes a pending memory request.

公开(公告)号：US20220318053A1

公开(公告)日：2022-10-06

申请号：US17698323

申请日：2022-03-18

Applicant: MemRay Corporation ,  Korea Advanced Institute of Science and Technology

Inventor： Myoungsoo Jung ,  Miryeong Kwon ,  Gyuyoung Park ,  Sangwon Lee

IPC: G06F9/48 ,  G06F9/4401 ,  G06F9/30 ,  G06F1/30 ,  G06F3/06

Abstract: A processor of the computing device includes a plurality of cores and executes one or more instructions stored in a memory module including a non-volatile memory, thereby performing a stop procedure upon a power failure and performing a go procedure upon power recovery. In the stop procedure, the processor accesses process control blocks of processes being run, scheduling each process to a run queue of a corresponding first core among first cores included in the cores, removes the scheduled process from the run queue and makes the removed process wait in a waiting queue, executes an idle task, and stops a device included in the computing device.

公开(公告)号：US12169636B2

公开(公告)日：2024-12-17

申请号：US18151645

申请日：2023-01-09

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo Jung ,  Miryeong Kwon ,  Donghyun Gouk

IPC: G06F3/06

Abstract: A computational storage supporting graph machine learning acceleration includes a solid state drive (SSD) configured to store a graph data set; and a field-programmable gate array (FPGA) configured to download, to a memory, a graph machine learning model programmed in a form of a data flow graph by a host, wherein a hardware logic built in the FPGA performs access to the SSD through a peripheral component interconnect-express (PCIe) switch.

公开(公告)号：US20240303122A1

公开(公告)日：2024-09-12

申请号：US18453702

申请日：2023-08-22

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo JUNG ,  Seungkwan Kang ,  Donghyun Gouk ,  Miryeong Kwon ,  Hyunkyu CHOI ,  Junhyeok Jang

IPC: G06F9/50 ,  G06F7/36

CPC classification number: G06F9/5027 ,  G06F7/36

Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a set-partitioning accelerator configured to sort each edge of an original graph stored in a coordinate list (COO) format by a node number, perform radix sorting based on a vertex identification (VID) to generate a COO array of a preset length, and perform uniform random sampling on some nodes of a given node array, a merger configured to merge the COO array of the preset length to generate one sorted COO array, a re-indexer configured to assign new consecutive VIDs respectively to the nodes selected through the uniform random sampling, and a compressed sparse row (CSR) converter configured to the edges sorted by the node number into a CSR format.

公开(公告)号：US20240281645A1

公开(公告)日：2024-08-22

申请号：US18450497

申请日：2023-08-16

Applicant: Korea Advanced Institute of Science and Technology

Inventor： Myoungsoo JUNG ,  Seungkwan Kang ,  Donghyun Gouk ,  Miryeong Kwon ,  Hyunkyu Choi ,  Junhyeok Jang

IPC: G06N3/0495

CPC classification number: G06N3/0495

Abstract: Provided is an apparatus for accelerating graph neural network (GNN) pre-processing, the apparatus including a conversion unit configured to convert an original graph in a coordinate list (COO) format into a graph in a compressed sparse row (CSR) format, a sub-graph generation unit configured to generate a sub-graph with a reduced degree of the graph in the CSR format, and an embedding table generation unit configured to generate an embedding table corresponding to the sub-graph.

公开(公告)号：US11689621B2

公开(公告)日：2023-06-27

申请号：US17561777

申请日：2021-12-24

Applicant: KOREA ADVANCED INSTITUTE OF SCIENCE AND TECHNOLOGY

Inventor： Myoungsoo Jung ,  Donghyun Gouk ,  Miryeong Kwon

IPC: H04L67/1097 ,  H04L69/08 ,  H04L67/60 ,  H04L67/568

CPC classification number: H04L67/1097 ,  H04L67/568 ,  H04L67/60 ,  H04L69/08

Abstract: A first IP address is set to the host, and a second IP address is set to the storage card. A storage card includes a storage device and a processor for executing firmware. The host converts a first Ethernet packet including an ISP-related request and destined for the second IP address into an NVMe request according to an NVMe protocol, and transfers the NVMe request to the storage card. The firmware parses the NVMe request to perform the ISP-related request.