公开(公告)号：US20170336198A1

公开(公告)日：2017-11-23

申请号：US15613119

申请日：2017-06-02

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Walter D. Mieher ,  Mark Ghinovker

IPC: G01B11/27 ,  G01N21/47 ,  G01N21/95 ,  G03F7/20 ,  H01L23/544 ,  H01L21/68

CPC classification number: G01B11/272 ,  G01N21/4785 ,  G01N21/9501 ,  G03F7/70633 ,  H01L21/68 ,  H01L21/682 ,  H01L23/544 ,  Y10S438/975

Abstract: Disclosed is a method for determining an overlay error between at least two layers in a multiple layer sample. An imaging optical system is used to measure multiple measured optical signals from multiple periodic targets on the sample, and the targets each have a first structure in a first layer and a second structure in a second layer. There are predefined offsets between the first and second structures A scatterometry overlay technique is used to analyze the measured optical signals of the periodic targets and the predefined offsets of the first and second structures of the periodic targets to thereby determine an overlay error between the first and second structures of the periodic targets. The scatterometry overlay technique is a phase based technique, and the imaging optical system is configured to have an illumination and/or collection numerical aperture (NA) and/or spectral band selected so that a specific diffraction order is collected and measured for the plurality of measured optical signals. In one aspect, the number of periodic targets equals half the number of unknown parameters.

公开(公告)号：US20160047744A1

公开(公告)日：2016-02-18

申请号：US14873120

申请日：2015-10-01

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Walter D. Mieher ,  Mark Ghinovker

IPC: G01N21/47 ,  G01N21/95

CPC classification number: G01B11/272 ,  G01N21/4785 ,  G01N21/9501 ,  G03F7/70633 ,  H01L21/68 ,  H01L21/682 ,  H01L23/544 ,  Y10S438/975

Abstract: Disclosed is a scatterometry mark for determining an overlay error, critical dimension, or profile of the mark. The mark includes a first plurality of periodic structures on a first layer, a second plurality of periodic structures on a second layer, and a third plurality of periodic structures on a third layer that is underneath the first and second layer. The third periodic structures are perpendicular to the first and second structures, and the third periodic structures have one or more characteristics so as to result in a plurality of lower structures beneath the third periodic structures being screened from significantly affecting at least part of a spectrum of a plurality of scattered signals detected from the first and second periodic structures for determining an overlay error, critical dimension, or profile of the first and second periodic structures or at least one of such detected scattered signals.

Abstract translation: 公开了用于确定标记的重叠误差，临界尺寸或轮廓的散射测量标记。 标记包括第一层上的第一多个周期性结构，第二层上的第二多个周期性结构以及位于第一和第二层下面的第三层上的第三多个周期性结构。 第三周期性结构垂直于第一和第二结构，并且第三周期结构具有一个或多个特性，以便导致第三周期结构下方的多个下部结构被屏蔽，从而显着影响至少部分频谱 从第一和第二周期结构检测的多个散射信号，用于确定第一和第二周期结构的重叠误差，临界尺寸或轮廓，或这些检测到的散射信号中的至少一个。

公开(公告)号：US20130293890A1

公开(公告)日：2013-11-07

申请号：US13898828

申请日：2013-05-21

Applicant: KLA-Tencor Corporation

Inventor： Nuriel Amir ,  Guy Cohen ,  Vladimir Levinski ,  Michael Adel

IPC: G01B11/14

CPC classification number: G01B11/14 ,  G03F7/70633 ,  G03F7/70683

Abstract: The disclosure is directed to designing and using an overlay target with orthogonal underlayer dummyfill. According to various embodiments, an overlay target may include one or more segmented overlay pattern elements forming at least one overlay target structure. The overlay target may further include one or more inactive pattern elements forming at least one dummyfill target structure. Each of the one or more inactive pattern elements may include dummyfill segmented along an axis orthogonal to a segmentation axis of at least one proximately disposed overlay pattern element. In some embodiments, each of the target structures or layers may be formed from a separate process layer successively disposed upon a substrate, such as a silicon wafer. In some embodiments, the overlay and dummyfill target structures may be twofold or fourfold rotationally symmetric to allow for certain manufacturing or metrology advantages.

Abstract translation: 本公开旨在设计和使用具有正交底层虚拟填充物的覆盖目标。 根据各种实施例，覆盖目标可以包括形成至少一个覆盖目标结构的一个或多个分段覆盖图案元素。 覆盖目标还可以包括形成至少一个虚拟填充目标结构的一个或多个无效模式元素。 一个或多个非活动图案元素中的每一个可以包括沿着与至少一个近似布置的覆盖图案元素的分割轴正交的轴分割的伪填充。 在一些实施例中，目标结构或层中的每一个可以由连续设置在诸如硅晶片的基底上的单独的处理层形成。 在一些实施例中，覆盖层和虚拟填充目标结构可以是双重的或四倍的旋转对称以允许某些制造或度量的优点。

公开(公告)号：US09910953B2

公开(公告)日：2018-03-06

申请号：US14356551

申请日：2014-03-04

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Tal Shusterman ,  Chen Dror ,  Ellis Chang

IPC: G06F17/50 ,  H01L21/66 ,  G03F1/36 ,  G03F7/20

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70625 ,  G03F7/70633 ,  G03F7/70683 ,  H01L22/12 ,  H01L22/30

Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.

公开(公告)号：US20180032662A1

公开(公告)日：2018-02-01

申请号：US15727477

申请日：2017-10-06

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Tal Shusterman ,  Chen Dror ,  Ellis Chang

IPC: G06F17/50 ,  G03F7/20 ,  G03F1/36 ,  H01L21/66

CPC classification number: G06F17/5081 ,  G03F1/36 ,  G03F7/70625 ,  G03F7/70633 ,  G03F7/70683 ,  H01L22/12 ,  H01L22/30

Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes. The target design device may further generate a target design library including a plurality of metrology targets that satisfy the metrology design rules for the metrology tool and the process design rules for the fabrication process, wherein the target design library includes specifications for fabricating the plurality of metrology targets using two or more process stages of the fabrication process based on the process design rules.

公开(公告)号：US09347879B2

公开(公告)日：2016-05-24

申请号：US14873120

申请日：2015-10-01

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Walter D. Mieher ,  Mark Ghinovker

IPC: H01L23/58 ,  G01N21/47 ,  G01N21/95

CPC classification number: G01B11/272 ,  G01N21/4785 ,  G01N21/9501 ,  G03F7/70633 ,  H01L21/68 ,  H01L21/682 ,  H01L23/544 ,  Y10S438/975

Abstract: Disclosed is a scatterometry mark for determining an overlay error, critical dimension, or profile of the mark. The mark includes a first plurality of periodic structures on a first layer, a second plurality of periodic structures on a second layer, and a third plurality of periodic structures on a third layer that is underneath the first and second layer. The third periodic structures are perpendicular to the first and second structures, and the third periodic structures have one or more characteristics so as to result in a plurality of lower structures beneath the third periodic structures being screened from significantly affecting at least part of a spectrum of a plurality of scattered signals detected from the first and second periodic structures for determining an overlay error, critical dimension, or profile of the first and second periodic structures or at least one of such detected scattered signals.

Abstract translation: 公开了用于确定标记的重叠误差，临界尺寸或轮廓的散射测量标记。 标记包括第一层上的第一多个周期性结构，第二层上的第二多个周期性结构以及位于第一和第二层下面的第三层上的第三多个周期性结构。 第三周期性结构垂直于第一和第二结构，并且第三周期结构具有一个或多个特性，以便导致第三周期结构下方的多个下部结构被屏蔽，从而显着影响至少部分频谱 从第一和第二周期结构检测的多个散射信号，用于确定第一和第二周期结构的重叠误差，临界尺寸或轮廓，或这些检测到的散射信号中的至少一个。

公开(公告)号：US20150112624A1

公开(公告)日：2015-04-23

申请号：US14588055

申请日：2014-12-31

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Leonid Poslavsky ,  John Fielden ,  John Madsen ,  Robert Peters

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metrology may be implemented during semiconductor device fabrication by a) modeling a first measurement on a first test cell formed in a layer of a partially fabricated device; b) performing a second measurement on a second test cell in the layer; c) feeding information from the second measurement into the modeling of the first measurement; and after a lithography pattern has been formed on the layer including the first and second test cells, d) modeling a third and a fourth measurement on the first and second test cells respectively using information from a) and b) respectively.

Abstract translation: 可以在半导体器件制造期间通过以下步骤来实现计量：a）对形成在部分制造的器件的层中的第一测试单元上的第一测量进行建模; b）对所述层中的第二测试单元执行第二测量; c）将第二测量中的信息馈送到第一测量的建模中; 并且在包括第一和第二测试单元的层上形成光刻图案之后，d）分别使用来自a）和b）的信息对第一和第二测试单元上的第三和第四测量进行建模。

公开(公告)号：US10387608B2

公开(公告)日：2019-08-20

申请号：US15727477

申请日：2017-10-06

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Tal Shusterman ,  Chen Dror ,  Ellis Chang

IPC: G06F17/50 ,  H01L21/66 ,  G03F1/36 ,  G03F7/20

Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes. The target design device may further generate a target design library including a plurality of metrology targets that satisfy the metrology design rules for the metrology tool and the process design rules for the fabrication process, wherein the target design library includes specifications for fabricating the plurality of metrology targets using two or more process stages of the fabrication process based on the process design rules.

公开(公告)号：US09559019B2

公开(公告)日：2017-01-31

申请号：US14588055

申请日：2014-12-31

Applicant: KLA-Tencor Corporation

Inventor： Michael Adel ,  Leonid Poslavsky ,  John Fielden ,  John Madsen ,  Robert Peters

IPC: H01L21/66

CPC classification number: H01L22/12 ,  H01L22/20 ,  H01L22/30 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Metrology may be implemented during semiconductor device fabrication by a) modeling a first measurement on a first test cell formed in a layer of a partially fabricated device; b) performing a second measurement on a second test cell in the layer; c) feeding information from the second measurement into the modeling of the first measurement; and after a lithography pattern has been formed on the layer including the first and second test cells, d) modeling a third and a fourth measurement on the first and second test cells respectively using information from a) and b) respectively.

Abstract translation: 可以在半导体器件制造期间通过以下步骤来实现计量：a）对形成在部分制造的器件的层中的第一测试单元上的第一测量进行建模; b）对所述层中的第二测试单元执行第二测量; c）将第二测量中的信息馈送到第一测量的建模中; 并且在包括第一和第二测试单元的层上形成光刻图案之后，d）分别使用来自a）和b）的信息对第一和第二测试单元上的第三和第四测量进行建模。

公开(公告)号：US10890436B2

公开(公告)日：2021-01-12

申请号：US13898828

申请日：2013-05-21

Applicant: KLA-Tencor Corporation

Inventor： Nuriel Amir ,  Guy Cohen ,  Vladimir Levinski ,  Michael Adel

IPC: G01B11/14 ,  G03F7/20

Abstract: The disclosure is directed to designing and using an overlay target with orthogonal underlayer dummyfill. According to various embodiments, an overlay target may include one or more segmented overlay pattern elements forming at least one overlay target structure. The overlay target may further include one or more inactive pattern elements forming at least one dummyfill target structure. Each of the one or more inactive pattern elements may include dummyfill segmented along an axis orthogonal to a segmentation axis of at least one proximately disposed overlay pattern element. In some embodiments, each of the target structures or layers may be formed from a separate process layer successively disposed upon a substrate, such as a silicon wafer. In some embodiments, the overlay and dummyfill target structures may be twofold or fourfold rotationally symmetric to allow for certain manufacturing or metrology advantages.