公开(公告)号：US20200090037A1

公开(公告)日：2020-03-19

申请号：US16299634

申请日：2019-03-12

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Kumiko NOMURA ,  Takao MARUKAME ,  Yoshifumi NISHI

IPC分类号： G06N3/08

摘要： According to an embodiment, a neural network device includes: a plurality of cores each executing computation and processing of a partial component in a neural network; and a plurality of routers transmitting data output from each core to one of the plurality of cores such that computation and processing are executed according to structure of the neural network. Each of the plurality of cores outputs at least one of a forward data and a backward data propagated through the neural network in a forward direction and a backward direction, respectively. Each of the plurality of routers is included in one of a plurality of partial regions each being a forward region or a backward region. A router included in the forward region and a router included in the backward region transmit the forward data and the backward data to other routers in the same partial regions, respectively.

公开(公告)号：US20180211154A1

公开(公告)日：2018-07-26

申请号：US15685042

申请日：2017-08-24

申请人： Kabushiki Kaisha Toshiba

发明人： Masafumi MORI ,  Takao MARUKAME ,  Tetsufumi TANAMOTO ,  Satoshi TAKAYA

IPC分类号： G06N3/04

CPC分类号： G06N3/0445 ,  G06N3/0472 ,  G06N3/063

摘要： According to an emboediment, a multiplier accumurator includes a controller, a high-order multiplier, a high-order accumulator, a low-order multiplier, and an output unit. The controller is configured to designate each digit within a range of the most significant digit in a coefficient for an input value to a stop digit as a target digit. The high-order multiplier is configured to calculate a high-order multiplication value by multiplying the input value, and a value and a weight of the target digit. The high-order accumulator is configured to calculate a high-order accumulation value by accumulatively adding the high-order multiplication values for input values. The low-order multiplier is configured to calculate a low-order multiplication value by multiplying an input value and a value of a digit smaller than the stop digit. The output unit is configured to output a value determined based on whether the high-order accumulation value exceeds a boundary value.

公开(公告)号：US20140227989A1

公开(公告)日：2014-08-14

申请号：US14108651

申请日：2013-12-17

申请人： Kabushiki Kaisha Toshiba

发明人： Masamichi SUZUKI ,  Hirotaka NISHINO ,  Kazuya Matsuzawa ,  Izumi HIRANO ,  Takao MARUKAME ,  Yusuke HIGASHI ,  Takahiro KURITA ,  Yuki SASAKI ,  Yuichiro MITANI

IPC分类号： H03M1/66 ,  H03D7/14 ,  H04B1/16 ,  H01L27/115

CPC分类号： H04B1/16 ,  H01L29/792 ,  H03D7/1441 ,  H03D7/1458 ,  H03M1/108 ,  H03M1/745

摘要： According to an embodiment, a semiconductor circuit includes a substrate, a tunnel oxide film, a charge storage film, a blocking layer, and plural nodes. The substrate is made of a semiconductor in which two diffusion layers each serving as either a source or a drain are formed. The tunnel oxide film is formed on a region of the substrate between the diffusion layers. The charge storage film is formed on the tunnel oxide layer and stores charge. The blocking layer is formed between the charge storage film and a gate electrode and has layers of a first oxide film, a nitride film and a second oxide film to have a thickness of 5 nm or larger but 15 nm or smaller. The nodes allow external application of voltages so that the source and the drain are reversed and allow detection a gate voltage, a drain current and a substrate current.

摘要翻译： 根据实施例，半导体电路包括衬底，隧道氧化物膜，电荷存储膜，阻挡层和多个节点。 衬底由其中形成有源极或漏极的两个扩散层的半导体构成。 隧道氧化膜形成在扩散层之间的衬底的区域上。 电荷存储膜形成在隧道氧化物层上并存储电荷。 阻挡层形成在电荷存储膜和栅电极之间，并且具有第一氧化膜，氮化物膜和第二氧化物膜的层，其厚度为5nm以上但为15nm以下。 节点允许外部施加电压，使得源极和漏极反向，并且允许检测栅极电压，漏极电流和衬底电流。

公开(公告)号：US20130250686A1

公开(公告)日：2013-09-26

申请号：US13762986

申请日：2013-02-08

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takao MARUKAME ,  Atsuhiro Kinoshita ,  Takahiro Kurita

IPC分类号： G11C16/08

CPC分类号： G11C16/08 ,  G06F12/0246 ,  G06F12/1018 ,  G06F2212/7201

摘要： According to an embodiment, a semiconductor memory device includes a first storage unit, a receiving unit, an acquiring unit, and an output control unit. The first storage unit is configured to store a value and address information in which a key address generated on the basis of a key associated with the value and a physical address of the value are associated with each other. The receiving unit is configured to receive a request for acquisition of the value associated with the key. The request contains the key. The acquiring unit is configured to acquire the physical address associated with the key address of the key contained in the request for acquisition on the basis of the address information. The output control unit is configured to acquire the value at the acquired physical address from the first storage unit and output the acquired value in response to the request.

摘要翻译： 根据实施例，半导体存储器件包括第一存储单元，接收单元，获取单元和输出控制单元。 第一存储单元被配置为存储其中基于与该值相关联的密钥和该值的物理地址相关联的密钥地址生成的密钥地址的值和地址信息。 接收单元被配置为接收用于获取与该密钥相关联的值的请求。 请求包含密钥。 获取单元被配置为基于地址信息获取与包含在获取请求中的密钥的地址相关联的物理地址。 输出控制单元被配置为从第一存储单元获取获取的物理地址处的值，并且响应于该请求而输出所获取的值。

公开(公告)号：US20240296325A1

公开(公告)日：2024-09-05

申请号：US18521665

申请日：2023-11-28

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Yoshifumi NISHI ,  Kumiko NOMURA ,  Takao MARUKAME ,  Koichi MIZUSHIMA

IPC分类号： G06N3/08 ,  G06N3/047 ,  G06N3/049 ,  G06N3/063

CPC分类号： G06N3/08 ,  G06N3/047 ,  G06N3/049 ,  G06N3/063

摘要： A neural network device according to an embodiment includes a plurality of neuron circuits, a plurality of synapse circuits, and a plurality of random number circuits. Each of the random number circuits outputs a random signal. Each of the synapse circuits receives the random signal from one of the random number circuits and updates a synaptic weight with a probability generated on the basis of the received random signal. The synapse circuits are divided into synapse groups. Each of two or more synapse circuits belonging to a first synapse group receives the random signal output from a first random number circuit. Each of two or more synapse circuits outputting output signals to a first neuron circuit belongs to a synapse group differing from a synapse group, to which other synapse circuits outputting the output signal to the first neuron circuit, belong.

公开(公告)号：US20230289581A1

公开(公告)日：2023-09-14

申请号：US18052086

申请日：2022-11-02

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takao MARUKAME ,  Kumiko NOMURA ,  Yoshifumi NISHI ,  Koichi MIZUSHIMA

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N3/049 ,  G06N3/044

CPC分类号： G06N3/063 ,  G06N3/08 ,  G06N3/049 ,  G06N3/044

摘要： According to an embodiment, an inference system includes a recurrent neural network circuit, an inference neural network, and a control circuit. The recurrent neural network circuit receives M input signals and outputs N intermediate signals, where M is an integer of 2 or more and N is an integer of 2 or more. The inference neural network circuit receives the N intermediate signals and outputs L output signals, where L is an integer of 2 or more. The control circuit adjusts a plurality of coefficients that are set to the recurrent neural network circuit and adjusts a plurality of coefficients that are set to the inference neural network circuit. The control circuit adjusts the coefficients set to the recurrent neural network circuit according to a total delay time period from timing for applying the M input signals until timing for firing the L output signals.

公开(公告)号：US20230079071A1

公开(公告)日：2023-03-16

申请号：US17891362

申请日：2022-08-19

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takao MARUKAME ,  Koichi MIZUSHIMA ,  Yoshifumi NISHI ,  Kumiko NOMURA

IPC分类号： G06N3/063 ,  H01L45/00 ,  G11C11/54 ,  G11C13/00

摘要： A variable resistance element according to an embodiment serves to change to a low resistance state or a high resistance state. The variable resistance element includes a first transition metal compound layer, a second transition metal compound layer, and a lithium ion conductor layer. The first transition metal compound layer is connected to a first electrode. The first transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The second transition metal compound layer is connected to a second electrode. The second transition metal compound layer is a metal compound containing lithium ions in lattice interstices. The lithium ion conductor layer is provided between the first transition metal compound layer and the second transition metal compound layer. The lithium ion conductor layer is a solid substance that is permeable to lithium ions and is less permeable to electrons.

公开(公告)号：US20220300792A1

公开(公告)日：2022-09-22

申请号：US17461440

申请日：2021-08-30

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Takao MARUKAME ,  Koichi MIZUSHIMA ,  Yoshifumi NISHI ,  Kumiko NOMURA

IPC分类号： G06N3/063 ,  G11C11/54 ,  G11C13/00 ,  G06N3/04 ,  G06N3/08

摘要： A memory device according to an embodiment can be used for storing weights for a neural network. An update circuit changes a difference between charge amounts accumulated in first/second accumulation circuits in the memory device. An output circuit outputs, as a weight, a signal corresponding to the difference between the charge amounts. The update circuit performs the change of the difference by changing, when the update amount is positive, the electric charges accumulated in the first accumulation circuit in a first direction by a charge amount corresponding to an absolute value of the update amount, the first direction being either an increasing direction or a decreasing direction, and changing, when the update amount is negative, the electric charges accumulated in the second accumulation circuit in the first direction by a charge amount corresponding to an absolute value of the update amount.

公开(公告)号：US20190156181A1

公开(公告)日：2019-05-23

申请号：US15909446

申请日：2018-03-01

申请人： Kabushiki Kaisha Toshiba

发明人： Takao MARUKAME ,  Kumiko NOMURA

IPC分类号： G06N3/04 ,  G06N3/08 ,  G06F7/544 ,  G06F17/16

摘要： According to an embodiment, a neural network device includes a control unit, and a matrix computation unit. The control unit causes a plurality of layers to execute a forward process of propagating a plurality of signal values in a forward direction, and a backward process of propagating a plurality of error values in a backward direction. The matrix computation unit performs computation on a plurality of values propagated in the plurality of layers. The matrix computation unit includes (m×n) multipliers, and an addition circuit. The (m×n) multipliers are provided in one-to-one correspondence with (m×n) coefficients included in a coefficient matrix of m rows and n columns. The addition circuit switches a pattern for adding values output from the respective (m×n) multipliers between the forward process and the backward process.

公开(公告)号：US20180082168A1

公开(公告)日：2018-03-22

申请号：US15444902

申请日：2017-02-28

申请人： Kabushiki Kaisha Toshiba

发明人： Takao MARUKAME ,  Jun DEGUCHI ,  Yoshifumi NISHI ,  Masamichi SUZUKI ,  Fumihiko TACHIBANA ,  Makoto MORIMOTO ,  Yuichiro MITANI

IPC分类号： G06N3/04 ,  H01L45/00

CPC分类号： H01L45/1233 ,  G06N3/049 ,  G06N3/0635 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/1266

摘要： A memcapacitor according to an embodiment includes a first electrode, a first dielectric layer provided on the first electrode, a plurality of variable resistance portions provided separately from each other on the first dielectric layer, a second dielectric layer provided on the first dielectric layer and between the variable resistance portions, and a second electrode provided on the variable resistance portions and the second dielectric layer. Each of the variable resistance portions is formed of a material that allows diffusion of metal atoms constituting the second electrode to inside of the variable resistance portion, and the second dielectric layer is formed of a material that prevents diffusion of the metal atoms constituting the second electrode to inside of the second dielectric layer.