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    DE-COUPLING CAPACITANCE PLACEMENT
    3.
    发明申请
    DE-COUPLING CAPACITANCE PLACEMENT 有权
    脱耦合电容放置

    公开(公告)号：US20170004239A1

    公开(公告)日：2017-01-05

    申请号：US14788819

    申请日：2015-07-01

    Applicant: International Business Machines Corporation

    Inventor： Harry Barowski ,  Joachim Keinert ,  Sourav Saha ,  Thomas Strach

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  G06F2217/82 ,  G06F2217/84

    Abstract: A method, executed by one or more processors, includes receiving IR-drop information as a function of location for a placement for a plurality of circuit blocks corresponding to an integrated circuit, calculating a target density for decoupling capacitors as a function of location based on the IR-drop information, placing a plurality of decoupling capacitors according to the target density to provide placed decoupling capacitors. The placed decoupling capacitors may be locally clustered to improve decoupling performance. The method may also include incrementally moving circuit elements or placed decoupling capacitors to avoid collisions within one or more circuit blocks, and routing the integrated circuit. A corresponding computer program product and computer system are also disclosed herein.

    Abstract translation: 一种由一个或多个处理器执行的方法包括：接收作为与集成电路相对应的多个电路块的放置位置的函数的IR投影信息，根据位置计算用于去耦电容器的目标密度，作为位置的函数 IR-drop信息，根据目标密度放置多个去耦电容器以提供放置的去耦电容器。 放置的去耦电容器可以局部聚集以改善去耦性能。 该方法还可以包括递增移动的电路元件或放置的去耦电容器以避免一个或多个电路块内的冲突，以及布线集成电路。 本文还公开了相应的计算机程序产品和计算机系统。

    DISCRETE ELECTRONIC DEVICE EMBEDDED IN CHIP MODULE
    4.
    发明申请
    DISCRETE ELECTRONIC DEVICE EMBEDDED IN CHIP MODULE 审中-公开

    公开(公告)号：US20190295938A1

    公开(公告)日：2019-09-26

    申请号：US16438736

    申请日：2019-06-12

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Andreas Huber ,  Harald Huels ,  Stefano S. Oggioni ,  Thomas Strach ,  Thomas-Michael Winkel

    IPC: H01L23/498 ,  H01L25/065 ,  H05K1/14 ,  H05K1/02 ,  H05K3/46 ,  H05K3/34 ,  H05K1/18 ,  H05K3/00 ,  H01L25/00 ,  H05K3/18 ,  H05K1/11

    Abstract: The invention relates to a method for embedding a discrete electronic device in a chip module. The chip module comprises a multilayer substrate which comprises a plurality of electrically conductive layers stacked above each other and an electrically non-conductive layer arranged between each pair of electrically conductive layers. The chip module is configured to receive one or more chips to be mounted onto a top surface thereof. Each electrically conductive layer comprises one or more electrically conductive structures. A recess is provided in a side surface of the chip module. The discrete electronic device is inserted into the recess. A first electrically conductive connection between a first electrical contact of the discrete electronic device and a first electrically conductive structure is established. Further, a second electrically conductive connection between a second electrical contact of the discrete electronic device and a second electrically conductive structure is established.

    Layout effect characterization for integrated circuits
    5.
    发明授权
    Layout effect characterization for integrated circuits 有权

    公开(公告)号：US10114914B2

    公开(公告)日：2018-10-30

    申请号：US15823712

    申请日：2017-11-28

    Applicant: International Business Machines Corporation

    Inventor： Martin Eckert ,  Thomas Gentner ,  Jens Kuenzer ,  Antje Mueller ,  Thomas Strach ,  Otto A. Torreiter

    IPC: G06F17/50

    Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.

    LAYOUT EFFECT CHARACTERIZATION FOR INTEGRATED CIRCUITS
    7.
    发明申请
    LAYOUT EFFECT CHARACTERIZATION FOR INTEGRATED CIRCUITS 审中-公开

    公开(公告)号：US20180107771A1

    公开(公告)日：2018-04-19

    申请号：US15823712

    申请日：2017-11-28

    Applicant: International Business Machines Corporation

    Inventor： Martin Eckert ,  Thomas Gentner ,  Jens Kuenzer ,  Antje Mueller ,  Thomas Strach ,  Otto A. Torreiter

    IPC: G06F17/50

    CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/84

    Abstract: A system for layout effect characterization of an integrated circuit includes a memory having computer readable instructions and a processor for executing the computer readable instructions. The computer readable instructions include selecting an adjustable clock setting of an input clock for a layout effect characterization circuit of the integrated circuit and enabling a predetermined duty cycle of the input clock to pass through a plurality of inverting device chains including a reference chain and one or more chains having a different inverting device arrangement and a same number of inverting devices per chain. The computer readable instructions also include measuring a captured output of the one or more chains having the different inverting device arrangement and a captured output of the reference chain.

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