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公开(公告)号：US20230044350A1
公开(公告)日：2023-02-09
申请号：US17394153
申请日：2021-08-04
发明人： BERNARD C. DRERUP , GUY L. GUTHRIE , JEFFREY A. STUECHELI , ALEXANDER MICHAEL TAFT , DEREK E. WILLIAMS
IPC分类号： G06F12/0811 , G06F12/0888 , G06F12/0891
摘要： A data processing system includes system memory and a plurality of processor cores each supported by a respective one of a plurality of vertical cache hierarchies. A first vertical cache hierarchy records information indicating communication of cache lines between the first vertical cache hierarchy and others of the plurality of vertical cache hierarchies. Based on selection of a victim cache line for eviction, the first vertical cache hierarchy determines, based on the recorded information, whether to perform a lateral castout of the victim cache line to another of the plurality of vertical cache hierarchies rather than to system memory and selects, based on the recorded information, a second vertical cache hierarchy among the plurality of vertical cache hierarchies as a recipient of the victim cache line via a lateral castout. Based on the determination, the first vertical cache hierarchy performs a castout of the victim cache line.
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2.发明申请公开(公告)号：US20230040617A1
公开(公告)日：2023-02-09
申请号：US17394195
申请日：2021-08-04
IPC分类号： G06F12/0831 , G06F12/0817 , G06F9/30
摘要： A data processing system includes a plurality of snoopers, a processing unit including master, and a system fabric communicatively coupling the master and the plurality of snoopers. The master sets a retry operating mode for an interconnect operation in one of alternative first and second operating modes. The first operating mode is associated with a first type of snooper, and the second operating mode is associated with a different second type of snooper. The master issues a memory access request of the interconnect operation on the system fabric of the data processing system. Based on receipt of a combined response representing a systemwide coherence response to the request, the master delays an interval having a duration dependent on the retry operating mode and thereafter reissues the memory access request on the system fabric.
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公开(公告)号：US20210216457A1
公开(公告)日：2021-07-15
申请号：US16742380
申请日：2020-01-14
IPC分类号： G06F12/0815
摘要： A data processing system includes multiple processing units all having access to a shared memory system. A processing unit includes a lower level cache configured to serve as a point of systemwide coherency and a processor core coupled to the lower level cache. The processor core includes an upper level cache, an execution unit that executes a store-conditional instruction to generate a store-conditional request that specifies a store target address and store data, and a flag that, when set, indicates the store-conditional request can be completed early in the processor core. The processor core also includes completion logic configured to commit an update of the shared memory system with the store data specified by the store-conditional request based on whether the flag is set.
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公开(公告)号：US20200264875A1
公开(公告)日：2020-08-20
申请号：US16278267
申请日：2019-02-18
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE
IPC分类号： G06F9/30 , G06F12/0815 , G06F12/084
摘要： A data processing system includes at least one processing unit and a memory controller coupled to a system memory. The processing unit includes a processor core and a cache memory including an arithmetic logic unit (ALU). The cache memory is configured to receive, from the processor core, an atomic memory operation (AMO) request specifying a target address of a data granule to be updated by an AMO and a location indication. Based on the location indication having a first setting, the AMO indicated by the AMO request is performed in the cache memory utilizing the ALU. Based on the location indication having a different second setting, the cache memory issues the AMO request to the memory controller to cause the AMO to be performed at the memory controller.
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公开(公告)号：US20200183585A1
公开(公告)日：2020-06-11
申请号：US16216587
申请日：2018-12-11
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE , HUGH SHEN
IPC分类号： G06F3/06 , G06F13/40 , G06F9/38 , G06F12/0831 , G06F12/0891
摘要： A data processing system includes a plurality of processor cores each having a respective associated cache memory, a memory controller, and a system memory coupled to the memory controller. A zero request of a processor core among the plurality of processor cores is transmitted on an interconnect fabric of the data processing system. The zero request specifies a target address of a target memory block to be zeroed has no associated data payload. The memory controller receives the zero request on the interconnect fabric and services the zero request by zeroing in the system memory the target memory block identified by the target address, such the target memory block is zeroed without caching the zeroed target memory block in the cache memory of the processor core.
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公开(公告)号：US20200151094A1
公开(公告)日：2020-05-14
申请号：US16184597
申请日：2018-11-08
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE , JOHN DODSON
IPC分类号： G06F12/0804
摘要： A data processing system includes a plurality of processing units and a system memory coupled to a memory controller. The system memory includes a persistent memory device and a non-persistent cache interposed between the memory controller and the persistent memory device. The memory controller receives a flush request of a particular processing unit among the plurality of processing units, the flush request specifying a target address. The memory controller, responsive to the flush request, ensures flushing of a target cache line of data identified by target address from the non-persistent cache into the persistent memory device.
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7.发明申请公开(公告)号：US20200034312A1
公开(公告)日：2020-01-30
申请号：US16049011
申请日：2018-07-30
发明人： DEREK E. WILLIAMS , GUY L. GUTHRIE , HUGH SHEN , SANJEEV GHAI
IPC分类号： G06F12/14 , G06F12/084
摘要： A data processing system includes multiple processing units all having access to a shared memory. A processing unit includes a processor core that executes memory access instructions including a store-conditional instruction that generates a store-conditional request specifying a store target address and store data. The processing unit further includes a reservation register that records shared memory addresses for which the processor core has obtained reservations and a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address. The processing unit additional includes a blocking state machine configured to protect the store target address against access by any conflicting memory access request during a protection window extension following servicing of the store-conditional request.
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8.发明申请公开(公告)号：US20190138630A1
公开(公告)日：2019-05-09
申请号：US15807828
申请日：2017-11-09
IPC分类号： G06F17/30
摘要： A technique for operating a data processing system that implements a split transaction coherency protocol that has an address tenure and a data tenure includes receiving, at a data source, a command (that includes an address tenure for requested data) that is issued from a data sink. The data source issues a response that indicates data associated with the address tenure is available to be transferred to the data sink during a data tenure. In response to determining that the data is available subsequent to issuing the response, the data source issues a first data packet to the data sink that includes the data during the data tenure. In response to determining that the data is not available subsequent to issuing the response, the data source issues a second data packet to the data sink that includes a data header that indicates the data is unavailable.
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公开(公告)号：US20190042486A1
公开(公告)日：2019-02-07
申请号：US15667270
申请日：2017-08-02
发明人： GUY L. GUTHRIE , CHARLES MARINO , PRAVEEN S. REDDY
IPC分类号： G06F13/16 , G06F12/0813 , G06F12/0811
摘要： A technique for operating a data processing system includes determining, by an arbiter of a processing unit of the data processing system, whether an over-commit has occurred. In response to determining that the over-commit has occurred, the arbiter selects a broadcast command to be dropped based on a number of hops traversed through the data processing system by the broadcast command.
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公开(公告)号：US20190042439A1
公开(公告)日：2019-02-07
申请号：US15668452
申请日：2017-08-03
IPC分类号： G06F12/0864 , G06F12/0815 , G06F12/0893
摘要： A set-associative cache memory includes a plurality of ways and a plurality of congruence classes. Each of the plurality of congruence classes includes a plurality of members each belonging to a respective one of the plurality of ways. In the cache memory, a data structure records a history of an immediately previous N ways from which cache lines have been evicted. In response to receipt of a memory access request specifying a target address, a selected congruence class among a plurality of congruence classes is selected based on the target address. At least one member of the selected congruence class is removed as a candidate for selection for victimization based on the history recorded in the data structure, and a member from among the remaining members of the selected congruence class is selected. The cache memory then evicts the victim cache line cached in the selected member of the selected congruence class.
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