公开(公告)号：US20160127191A1

公开(公告)日：2016-05-05

申请号：US14531008

申请日：2014-11-03

Applicant: Intel Corporation

Inventor： Mohan K. Nair

IPC: H04L12/24

CPC classification number: H04L41/12

Abstract: In one embodiment, a system comprises: a plurality of compute nodes having a first core, a first memory, and a first fabric; a plurality of input/output (I/O) nodes having a second core, a second memory, and a second fabric and to couple to one or more I/O devices; at least one management node to receive discovery information responsive to execution of a discovery process by the plurality of compute nodes and the plurality of I/O nodes. The discovery information may include resource request information from the plurality of compute nodes and resource availability information from the plurality of I/O nodes. The at least one management node may configure the plurality of compute nodes and the plurality of I/O nodes based thereon. The system may further include an interconnection fabric to couple the plurality of compute nodes, the plurality of I/O nodes, and the at least one management node, where the at least one management node is to enable the one or more I/O devices to be shared between at least some of the plurality of compute nodes based on the discovery information. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，系统包括：具有第一核心，第一存储器和第一织物的多个计算节点; 具有第二核心，第二存储器和第二结构的多个输入/输出（I / O）节点并且耦合到一个或多个I / O设备; 至少一个管理节点，用于响应于所述多个计算节点和所述多个I / O节点的发现过程的执行来接收发现信息。 发现信息可以包括来自多个计算节点的资源请求信息和来自多个I / O节点的资源可用性信息。 基于此，至少一个管理节点可以配置多个计算节点和多个I / O节点。 该系统可以进一步包括互连结构以耦合多个计算节点，多个I / O节点和至少一个管理节点，其中至少一个管理节点要使一个或多个I / O设备 基于所述发现信息在所述多个计算节点中的至少一些计算节点之间共享。 描述和要求保护其他实施例。

公开(公告)号：US20180276394A1

公开(公告)日：2018-09-27

申请号：US15470270

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Mohan K. Nair ,  Rajesh M. Sankaran ,  Utkarsh Y. Kakaiya ,  Zhenfu Chai ,  David M. Lee ,  Pratik M. Marolia

IPC: G06F21/60 ,  H04L29/08 ,  G06F9/44 ,  G06F12/0811

CPC classification number: G06F21/602 ,  G06F9/4403 ,  G06F9/4406 ,  G06F9/4408 ,  G06F12/0815 ,  G06F13/4282 ,  G06F21/575 ,  G06F21/85 ,  G06F2212/1052 ,  G06F2213/0026 ,  H04L63/04

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.

公开(公告)号：US20160283433A1

公开(公告)日：2016-09-29

申请号：US14669295

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mohan K. Nair ,  Brent D. Thomas ,  Ramamurthy Krithivas

IPC: G06F13/42 ,  G06F13/40 ,  G06F9/44

CPC classification number: G06F13/4282 ,  G06F9/4411 ,  G06F13/4022 ,  G06F13/4068

Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，节点包括独立执行指令的至少一个核心; 用于从所述至少一个核心接收信息并将所述信息包括在第一通信协议的第一分组中的第一主机设备; 耦合到所述第一主机设备以接收所述第一分组并且将所述第一分组提供给转换逻辑或第一接口以经由所述第一通信协议的第一互连与第一设备通信的选择逻辑; 所述转换逻辑在选择逻辑选择下接收第一分组，并将第一分组封装成第二通信协议的第二分组; 以及耦合到所述转换逻辑以接收所述第二分组并经由所述第二通信协议的第二互连将所述第二分组传送到第二设备的第二接口。 描述和要求保护其他实施例。

公开(公告)号：US09984017B2

公开(公告)日：2018-05-29

申请号：US14583682

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Mohan K. Nair

IPC: G06F13/36 ,  G06F13/366 ,  G06F13/40 ,  G06F13/42

CPC classification number: G06F13/366 ,  G06F13/4068 ,  G06F13/4282

Abstract: This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device.

公开(公告)号：US09817787B2

公开(公告)日：2017-11-14

申请号：US14669295

申请日：2015-03-26

Applicant: Intel Corporation

Inventor： Mohan K. Nair ,  Brent D. Thomas ,  Ramamurthy Krithivas

IPC: G06F13/14 ,  G06F13/36 ,  H05K7/10 ,  G06F13/42 ,  G06F9/44 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F9/4411 ,  G06F13/4022 ,  G06F13/4068

Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.

公开(公告)号：US09774503B2

公开(公告)日：2017-09-26

申请号：US14531008

申请日：2014-11-03

Applicant: Intel Corporation

Inventor： Mohan K. Nair

IPC: G06F15/173 ,  H04L12/24

CPC classification number: H04L41/12

Abstract: In one embodiment, a system comprises: a plurality of compute nodes having a first core, a first memory, and a first fabric; a plurality of input/output (I/O) nodes having a second core, a second memory, and a second fabric and to couple to one or more I/O devices; at least one management node to receive discovery information responsive to execution of a discovery process by the plurality of compute nodes and the plurality of I/O nodes. The discovery information may include resource request information from the plurality of compute nodes and resource availability information from the plurality of I/O nodes. The at least one management node may configure the plurality of compute nodes and the plurality of I/O nodes based thereon. The system may further include an interconnection fabric to couple the plurality of compute nodes, the plurality of I/O nodes, and the at least one management node, where the at least one management node is to enable the one or more I/O devices to be shared between at least some of the plurality of compute nodes based on the discovery information. Other embodiments are described and claimed.

公开(公告)号：US09753875B2

公开(公告)日：2017-09-05

申请号：US15001330

申请日：2016-01-20

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Mohan K. Nair ,  Joseph Murray ,  Rohit R. Verma ,  Gary J. Lavelle ,  Robert P. Adler

IPC: G06F13/364 ,  H04L12/28 ,  H04L12/54 ,  H04L12/701 ,  H04L12/761 ,  G06F15/78 ,  G06F13/38 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/385 ,  G06F13/4265 ,  G06F15/7807 ,  G06F15/7825 ,  G06F2213/0038 ,  H04L12/28 ,  H04L12/54 ,  H04L45/00 ,  H04L45/16

Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

公开(公告)号：US20160188513A1

公开(公告)日：2016-06-30

申请号：US14583682

申请日：2014-12-27

Applicant: Intel Corporation

Inventor： Mohan K. Nair

IPC: G06F13/366 ,  G06F13/42 ,  G06F13/40

CPC classification number: G06F13/366 ,  G06F13/4068 ,  G06F13/4282

Abstract: This disclosure pertains to an intelligent network fabric used to connect multiple computer nodes with one or more SR-IOV devices. The intelligent fabric includes a management device and a network fabric coupled thereto. A plurality of virtual endpoint devices are coupled to the network fabric and are configured to connect with a plurality of compute nodes. In addition, the intelligent network fabric includes a root port device coupled to the network fabric which the root port is configured to connect with virtual functions within a SR-IOV device.

Abstract translation: 本公开涉及用于将多个计算机节点与一个或多个SR-IOV设备连接的智能网络结构。 智能结构包括管理设备和与其耦合的网络结构。 多个虚拟端点设备耦合到网络结构并且被配置为与多个计算节点连接。 此外，智能网络结构包括耦合到网络结构的根端口设备，其根端口被配置为与SR-IOV设备内的虚拟功能相连接。

公开(公告)号：US10789370B2

公开(公告)日：2020-09-29

申请号：US15470270

申请日：2017-03-27

Applicant: INTEL CORPORATION

Inventor： Mohan K. Nair ,  Rajesh M. Sankaran ,  Utkarsh Y. Kakaiya ,  Zhenfu Chai ,  David M. Lee ,  Pratik M. Marolia

IPC: G06F9/4401 ,  G06F21/60 ,  G06F21/85 ,  G06F21/57 ,  G06F12/0815 ,  G06F13/42 ,  H04L29/06

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.

公开(公告)号：US20160132447A1

公开(公告)日：2016-05-12

申请号：US15001330

申请日：2016-01-20

Applicant: Intel Corporation

Inventor： Sridhar Lakshmanamurthy ,  Mikal C. Hunsaker ,  Michael T. Klinglesmith ,  Blaise Fanning ,  Mohan K. Nair ,  Joseph Murray ,  Rohit R. Verma ,  Gary J. Lavelle ,  Robert P. Adler

IPC: G06F13/364 ,  G06F13/42

CPC classification number: G06F13/364 ,  G06F13/385 ,  G06F13/4265 ,  G06F15/7807 ,  G06F15/7825 ,  G06F2213/0038 ,  H04L12/28 ,  H04L12/54 ,  H04L45/00 ,  H04L45/16

Abstract: In one embodiment, the present invention includes a method for receiving a request in a router from a first endpoint coupled to the router, where the request is for an aggregated completion. In turn, the router can forward the request to multiple target agents, receive a response from each of the target agents, and consolidate the responses into an aggregated completion. Then, the router can send the aggregated completion to the first endpoint. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于从耦合到路由器的第一端点在路由器中接收请求的方法，其中该请求用于聚合完成。 反过来，路由器可以将请求转发到多个目标代理，从每个目标代理接收响应，并将响应合并到聚合完成中。 然后，路由器可以将聚合完成发送到第一个端点。 描述和要求保护其他实施例。